MC10EP52, MC100EP52 3.3 V / 5 VECL Differential Data and Clock D FlipFlop Description The MC10EP/100EP52 is a differential data, differential clock D www.onsemi.com flip-flop. The device is pin and functionally equivalent to the EL52 device. Data enters the master portion of the flipflop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a 8 8 positive transition of the clock. The differential clock inputs of the 1 1 EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input SOIC8 NB TSSOP8 DFN8 conditions (pulled down to V ) the outputs of the device will remain D SUFFIX DT SUFFIX MN SUFFIX EE CASE 75107 CASE 948R02 CASE 506AA stable. The 100 Series contains temperature compensation. MARKING DIAGRAMS* Features 330 ps Typical Propagation Delay 8 8 Maximum Frequency = 4 GHz Typical HEP01 PECL Mode: V = 3.0 V to 5.5 V with V = 0 V CC EE HP01 ALYW ALYW NECL Mode: V = 0 V with V = 3.0 V to 5.5 V CC EE 14 1 Open Input Default State 1 Safety Clamp on Inputs 8 8 Q Output Will Default LOW with Inputs Open or at V EE KEP01 KP01 These Devices are Pb-Free, Halogen Free and are RoHS Compliant ALYW ALYW 14 1 1 SOIC8 NB TSSOP8 DFN8 H = MC10 A = Assembly Location K = MC100 L = Wafer Lot 5T = MC10 Y = Year 3O = MC100 W = Work Week M = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2016 Rev. 8 MC10EP52/D 3OM 5T M MC10EP52, MC100EP52 Table 1. PIN DESCRIPTION D 1 8 V CC PIN FUNCTION CLK*, CLK* ECL Clock Inputs D*, D* ECL Data Input D D 2 7 Q Q, Q ECL Data Outputs V Positive Supply CC Flip-Flop V Negative Supply EE CLK 3 6 Q EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. CLK45 V EE * Pins will default LOW when left open. Table 2. TRUTH TABLE Figure 1. 8-Lead Pinout (Top View) and Logic Diagram D CLK Q L Z L H Z H Z = LOW to HIGH Transition Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8 NB Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 155 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2