MC10LVEP16, MC100LVEP16
2.5V / 3.3VECL
Differential Receiver/Driver
Description
The MC10/100LVEP16 is a world class differential receiver/driver.
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The device is functionally equivalent to the EL16, EP16 and LVEL16
devices. With output transition times significantly faster than the EL16
and LVEL16, the LVEP16 is ideally suited for interfacing with high
frequency and low voltage (2.5 V) sources. Single-Ended CLK input
8
8
operation is limited to a V 3.0 V in PECL mode, or V 3.0 V in
CC EE
1
1
NECL mode.
SOIC8 NB TSSOP8 DFN8
The V pin, an internally generated Voltage supply, is available to
BB
D SUFFIX DT SUFFIX MN SUFFIX
this device only. For Single-Ended input conditions, the unused
CASE 75107 CASE 948R02 CASE 506AA
differential input is connected to V as a switching reference voltage.
BB
V may also rebias AC coupled inputs. When used, decouple V
BB BB
and V via a 0.01 F capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
BB
MARKING DIAGRAMS*
The 100 Series contains temperature compensation.
8
8
Features
HVP16
HU16
240 ps Propagation Delay
ALYW
ALYW
Maximum Frequency = > 4 GHz Typical
14
1
1
PECL Mode Operating Range:
V = 2.375 V to 3.8 V with V = 0 V
CC EE
8 8
NECL Mode Operating Range:
KVP16
KU16
V = 0 V with V = 2.375 V to 3.8 V
CC EE
ALYW
ALYW
V Output
BB
14
1
1
Open Input Default State
SOIC8 NB TSSOP8 DFN8
LVDS Input Compatible
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5Y = MC10 Y = Year
4L = MC100 W = Work Week
M = Date Code = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
August, 2016 Rev. 12 MC10LVEP16/D
4L M 5Y M
MC10LVEP16, MC100LVEP16
Table 1. PIN DESCRIPTION
1 8
NC V
CC
Pin Function
D*, D** ECL Data Inputs
D 2 7 Q
Q, Q ECL Data Outputs
V Ref. Voltage Output
BB
V Positive Supply
CC
D 3 6 Q
V Negative Supply
EE
NC No Connect
V45 V
BB EE
EP (DFN8 only) Thermal exposed pad must
be connected to a sufficient thermal con-
duit. Electrically connect to the most neg-
ative supply (GND) or leave unconnec-
Figure 1. 8-Lead Pinout (Top View) and Logic
ted, floating open.
Diagram
* Pins will default LOW when left open.
**Pins will default to V /2 when left open.
CC
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 k
Internal Input Pullup Resistor 37.5 k
ESD Protection
> 4 kV
Human Body Model
> 200 V
Machine Model
> 2 kV
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC8 NB NB Level 1
Level 3
TSSOP8
Level 1
DFN8
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2