MC74HC164B 8-Bit Serial-Input/Parallel- Output Shift Register HighPerformance SiliconGate CMOS The MC74HC164B is identical in pinout to the LS164. The device www.onsemi.com inputs are compatible with standard CMOS outputs with pullup resistors, they are compatible with LSTTL outputs. MARKING The MC74HC164B is an 8bit, serialinput to paralleloutput shift DIAGRAMS register. Two serial data inputs, A1 and A2, are provided so that one input may be used as a data enable. Data is entered on each rising edge 14 of the clock. The activelow asynchronous Reset overrides the Clock SOIC14 HC164BG 14 D SUFFIX and Serial Data inputs. Schmitttrigger action at the Clock input AWLYWW CASE 751A 1 enhances the devices tolerance to slower rise and fall times and 1 immunity to noise of the input clock signal. Features 14 Output Drive Capability: 10 LSTTL Loads HC TSSOP14 14 164B DT SUFFIX Outputs Directly Interface to CMOS, NMOS, and TTL ALYW CASE 948G 1 Operating Voltage Range: 2.0 V to 6.0 V 1 Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices A = Assembly Location In Compliance with the JEDEC Standard No. 7 A Requirements L, WL = Wafer Lot Chip Complexity: 244 FETs or 61 Equivalent Gates Y = Year NLV Prefix for Automotive and Other Applications Requiring W, WW = Work Week G or = PbFree Package Unique Site and Control Change Requirements AECQ100 (Note: Microdot may be in either location) Qualified and PPAP Capable These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2016 Rev. 2 MC74HC164B/DMC74HC164B PIN ASSIGNMENT LOGIC DIAGRAM 3 1 Q A1 1 14 V A SERIAL CC A1 4 DATA DATA Q A2 2 13 Q 2 B H INPUTS A2 5 Q C Q 3 12 Q A G 6 PARALLEL Q D Q 4 11 Q B F DATA 10 Q E OUTPUTS Q 5 10 Q C E 11 Q F Q 6 9 RESET D 12 8 Q G CLOCK GND 7 8 CLOCK 13 Q H 9 PIN 14 = V CC RESET PIN 7 = GND FUNCTION TABLE Inputs Outputs Reset Clock A1 A2 Q Q Q A B H LX X X L L L H X X No Change H HDD Q Q An Gn H DHD Q Q An Gn D = data input Q Q = data shifted from the preceding An Gn stage on a rising edge at the clock input. ORDERING INFORMATION Device Package Shipping MC74HC164BDG 55 Units / Rail SOIC14 MC74HC164BDR2G 2500 / Tape & Reel (PbFree) NLV74HC164BDR2G* 2500 / Tape & Reel MC74HC164BDTR2G 2500 / Tape & Reel TSSOP14 (PbFree) NLV74HC164BDTR2G* 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable www.onsemi.com 2