MC74LCX244MNTWG ON Semiconductor

MC74LCX244 Octal Buffer, Non-Inverting, Low Voltage, 3-State The MC74LCX244 is a high performance, noninverting octal buffer operating from a 2.3 to 5.5 V supply. High impedance TTL www.onsemi.com compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V specification of 5.5 V allows MC74LCX244 inputs I to be safely driven from 5 V devices. The MC74LCX244 is suitable for memory address driving and all TTL level bus oriented transceiver applications. SOIC20 WB TSSOP20 QFN20 Current drive capability is 24 mA at the outputs. The Output Enable DW SUFFIX DT SUFFIX MN SUFFIX (OE) input, when HIGH, disables the output by placing them in CASE 751D CASE 948E CASES 485AA a HIGH Z condition. & 485CB Features MARKING DIAGRAMS Designed for 2.3 to 5.5 V V Operation CC 20 5 V Tolerant Interface Capability With 5 V TTL Logic Supports Live Insertion and Withdrawal LCX244 AWLYYWWG I Specification Guarantees High Impedance When V = 0 V OFF CC LVTTL Compatible 1 LVCMOS Compatible SOIC20 WB 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 A) 20 Substantially Reduces System Power Requirements LCX Latchup Performance Exceeds 500 mA 244 ALYW ESD Performance: Human Body Model >2000 V 1 Machine Model >200 V TSSOP20 NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 1 1 Qualified and PPAP Capable LCX These Devices are PbFree, Halogen Free/BFR Free and are RoHS 244 244 Compliant ALYW ALYW QFN20 485AA QFN20 485CB A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: October, 2017 Rev. 20 MC74LCX244/DMC74LCX244 1 V 2OE 1O0 2D0 1O1 2D1 1O2 2D2 1O3 2D3 CC 1OE 20 19 18 17 16 15 14 13 12 11 2 18 1D0 1O0 4 16 1D1 1O1 6 14 1D2 1O2 1 2 3 4567 9 8 10 1OE 1D0 2O0 1D1 2O1 1D2 2O2 1D3 2O3 GND 8 12 1D3 1O3 19 12 19 20 11 2OE QFN PIN 1 10 17 3 2D0 2O0 29 15 5 2D1 2O1 Figure 1. Pinouts: 20Lead (Top View) 13 7 2D2 2O2 PIN NAMES 11 9 2D3 2O3 PINS FUNCTION nOE Output Enable Inputs Figure 2. Logic Diagram 1Dn, 2Dn Data Inputs 1On, 2On 3State Outputs TRUTH TABLE INPUTS OUTPUTS 1OE 1Dn 1On, 2On 2OE 2Dn L L L L H H H X Z H = High Voltage Level L = Low Voltage Level Z = High Impedance State X = High or Low Voltage Level and Transitions are Acceptable For I reasons, DO NOT FLOAT Inputs CC www.onsemi.com 2