MC74LCX574 Low-Voltage CMOS Octal D-Type Flip-Flop Flow Through Pinout With 5 VTolerant Inputs and Outputs www.onsemi.com (3State, NonInverting) MARKING The MC74LCX574 is a high performance, noninverting octal DIAGRAMS Dtype flipflop operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current 20 loading to input drivers while TTL compatible outputs offer improved LCX574 switching noise performance. A V specification of 5.5 V allows I AWLYYWWG MC74LCX574 inputs to be safely driven from 5.0 V devices. SOIC20 WB DW SUFFIX The MC74LCX574 consists of 8 edgetriggered flipflops with 1 CASE 751D individual Dtype inputs and 3state true outputs. The buffered clock and buffered Output Enable (OE) are common to all flipflops. The eight flipflops will store the state of individual D inputs that meet the setup and hold time requirements on the LOWtoHIGH Clock (CP) LCX transition. With the OE LOW, the contents of the eight flipflops are 574 available at the outputs. When the OE is HIGH, the outputs go to the ALYW TSSOP20 high impedance state. The OE input level does not affect the operation DT SUFFIX of the flipflops. The LCX574 flow through design facilitates easy PC CASE 948E board layout. A = Assembly Location Features L, WL = Wafer Lot Y, YY = Year Designed for 2.3 to 3.6 V V Operation CC W, WW = Work Week 5 V Tolerant Interface Capability With 5 V TTL Logic G or = PbFree Package Supports Live Insertion and Withdrawal (Note: Microdot may be in either location) I Specification Guarantees High Impedance When V = 0 V OFF CC LVTTL Compatible LVCMOS Compatible ORDERING INFORMATION See detailed ordering and shipping information in the package 24mA Balanced Output Sink and Source Capability dimensions section on page 6 of this data sheet. Near Zero Static Supply Current in All Three Logic States (10 A) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: Human Body Model >2000 V Machine Model >200 V NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: December, 2014 Rev. 10 MC74LCX574/DMC74LCX574 1 OE 11 CP 19 CP O0 2 Q D0 D 18 CP 3 O1 Q V O0 O1 O2 O3 O4 O5 O6 O7 CP CC D1 D 20 19 18 17 16 15 14 12 13 11 17 CP 4 O2 Q D2 D 16 CP 5 O3 Q D3 D 1 2 3456 7 8 9 10 OE D0 D1 D2 D3 D4 D5 D6 D7 GND 15 CP 6 O4 Q Figure 1. Pinout: 20Lead (Top View) D4 D 14 CP 7 O5 Q PIN NAMES D5 D Pins Function 13 CP OE Output Enable Input 8 O6 Q CP Clock Pulse Input D6 D D0D7 Data Inputs 12 O0O7 3State Outputs CP 9 O7 Q D7 D Figure 2. Logic Diagram TRUTH TABLE INTERNAL LATCHES INPUTS OUTPUTS OE CP Dn Q On OPERATING MODE L l L L Load and Read Register L h H H L X NC NC Hold and Read Register H X NC Z Hold and Disable Outputs H l L Z Load Internal Register and Disable Outputs H h H Z H = High Voltage Level h = High Voltage Level One Setup Time Prior to the LowtoHigh Clock Transition L = Low Voltage Level l = Low Voltage Level One Setup Time Prior to the LowtoHigh Clock Transition NC = No Change X = High or Low Voltage Level and Transitions are Acceptable Z = High Impedance State = LowtoHigh Transition = Not a LowtoHigh Transition For I Reasons, DO NOT FLOAT Inputs CC www.onsemi.com 2