MC74VHC74 Dual D-Type Flip-Flop with Set and Reset The MC74VHC74 is an advanced high speed CMOS Dtype flipflop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL www.onsemi.com while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output MARKING during the positive going transition of the Clock pulse. DIAGRAMS Reset (RD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low. 14 The internal circuit is composed of three stages, including a buffer SOIC14 VHC74G D SUFFIX output which provides high noise immunity and stable output. The 14 AWLYWW CASE 751A inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V 1 1 systems to 3.0 V systems. 14 Features VHC High Speed: f = 170MHz (Typ) at V = 5V TSSOP14 max CC 74 DT SUFFIX Low Power Dissipation: I = 2 A (Max) at T = 25C CC A ALYW CASE 948G 1 High Noise Immunity: V = V = 28% V NIH NIL CC 1 Power Down Protection Provided on Inputs Balanced Propagation Delays A = Assembly Location WL, L = Wafer Lot Designed for 2.0 V to 5.5 V Operating Range Y, YY = Year Low Noise: V = 0.8 V (Max) OLP WW, W = Work Week G or = PbFree Package Pin and Function Compatible with Other Standard Logic Families (Note: Microdot may be in either location) Latchup Performance Exceeds 300 mA ESD Performance: FUNCTION TABLE Human Body Model > 2000 V Inputs Outputs Machine Model > 200 V SD RD CP D Q Q Chip Complexity: 128 FETs or 32 Equivalent Gates LH X X HL NLV Prefix for Automotive and Other Applications Requiring HL X X LH Unique Site and Control Change Requirements AECQ100 L L X X H* H* Qualified and PPAP Capable HH H H L HH L L H These Devices are PbFree, Halogen Free/BFR Free and are RoHS H H L X No Change Compliant H H H X No Change H H X No Change *Both outputs will remain high as long as Set and Re- 13 1 RD1 RD2 set are low, but the output states are unpredictable if Set and Reset go high simultaneously. 9 5 2 12 D1 D2 Q2 Q1 6 8 3 11 ORDERING INFORMATION Q1 CP1 CP2 Q2 See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. 4 10 SD1 SD2 Figure 1. LOGIC DIAGRAM Semiconductor Components Industries, LLC, 2011 1 Publication Order Number: April, 2019 Rev. 9 MC74VHC74/DMC74VHC74 RD1 1 14 V CC D1 2 13 RD2 CP1 3 12 D2 SD1 4 11 CP2 Q1 5 10 SD2 Q1 6 9 Q2 GND 7 8 Q2 Figure 2. PIN ASSIGNMENT MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protection circuitry to guard against damage V DC Supply Voltage 0.5 to + 7.0 V CC due to high static voltages or electric V DC Input Voltage 0.5 to + 7.0 V fields. However, precautions must in be taken to avoid applications of any V DC Output Voltage 0.5 to V + 0.5 V out CC voltage higher than maximum rated I Input Diode Current 20 mA voltages to this highimpedance cir- IK cuit. For proper operation, V and in I Output Diode Current 20 mA OK V should be constrained to the out I DC Output Current, per Pin 25 mA range GND (V or V ) V . in out CC out Unused inputs must always be I DC Supply Current, V and GND Pins 50 mA CC CC tied to an appropriate logic voltage level (e.g., either GND or V ). P Power Dissipation in Still Air, SOIC Packages 500 mW CC D 450 Unused outputs must be left open. TSSOP Package T Storage Temperature 65 to +150 C stg Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating SOIC Packages: 7 mW/ C from 65 to 125 C TSSOP Package: 6.1 mW/ C from 65 to 125 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V DC Supply Voltage 2.0 5.5 V CC V DC Input Voltage 0 5.5 V in V DC Output Voltage 0 V V out CC T Operating Temperature, All Package Types 55 + 125 C A t , t Input Rise and Fall Time V = 3.3V 0.3V 0 100 ns/V r f CC 0 20 V =5.0V 0.5V CC www.onsemi.com 2