MC74VHCT50ADTR2G ON Semiconductor

MC74VHCT50A Noninverting Buffer / CMOS Logic Level Shifter with LSTTLCompatible Inputs The MC74VHCT50A is a hex noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation MC74VHCT50A MAXIMUM RATINGS Symbol Parameter Value Unit V DC Supply Voltage 0.5 to 7.0 V CC V DC Input Voltage 0.5 V 7.0 V IN I V DC Output Voltage Output in HIGH or LOW State 0.5 V 7.0 V OUT O I DC Input Diode Current 20 mA IK I DC Output Diode Current 20 mA OK I DC Output Source/Sink Current 25 mA O I DC Supply Current per Supply Pin 50 mA CC I DC Ground Current per Ground Pin 50 mA GND T Storage Temperature Range 65 to 150 C STG T Lead Temperature, 1 mm from Case for 10 Seconds 260 C L T Junction Temperature under Bias 150 C J Thermal Resistance (Note 1) C/W JA SOIC 125 TSSOP 170 P Power Dissipation in Still Air mW D SOIC 500 TSSOP 450 V ESD Withstand Voltage Human Body Model (Note 2) > 2000 V ESD Machine Model (Note 3) > 200 Charged Device Model (Note 4) 2000 I LatchUp Performance Above V and Below GND at 85 C (Note 5) 300 mA LatchUp CC Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mmby1 inch, 2ounce copper trace with no air flow. 2. Tested to EIA/JESD22A114A. 3. Tested to EIA/JESD22A115A. 4. Tested to JESD22C101A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit DC Supply Voltage V 2.0 5.5 V CC DC Input Voltage V 0.0 5.5 V IN DC Output Voltage V = 0 V 0.0 5.5 V CC OUT High or Low State 0.0 V CC Operating Temperature Range T 55 +125 C A Input Rise and Fall Time V = 3.3 V 0.3 V t , t 0 100 ns/V CC r f V = 5.0 V 0.5 V 0 20 CC Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. TEST POINT 3.0V OUTPUT 50% A DEVICE GND UNDER t t PLH PHL C * L TEST V OH 50% V CC Y V OL *Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit