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They possess Wide operating voltage range: 2 to 6 volts the high noise immunity and low power consumption of Low input current: 1 PA maximum standard CMOS integrated circuits, as well as the ability to Low quiescent current: 80 PA maximum (74 Series) drive 15 LS-TTL loads. Due to the large output drive capa- bility and the 3-STATE feature, these devices are ideally Output drive capability: 15 LS-TTL loads suited for interfacing with bus lines in a bus organized sys- tem. When the LATCH ENABLE input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again. When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function, and pin-out com- patible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V and ground. CC Ordering Code: Order Number Package Number Package Description MM74HC373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Truth Table Output Latch Data 373 Pin Assignments for DIP, SOIC, SOP and TSSOP Control Enable Output L HHH LH L L LL X Q 0 HX X Z H HIGH Level L LOW Level Q Level of output before steady-state input conditions were established. 0 Z High Impedance Top View 2005 Fairchild Semiconductor Corporation DS005335 www.fairchildsemi.com