MM74HC4049 MM74HC4050 Hex Inverting Logic Level Down Converter Hex Logic Level Down Converter February 1984 Revised October 1999 MM74HC4049 MM74HC4050 Hex Inverting Logic Level Down Converter Hex Logic Level Down Converter ple buffer or inverter without level translation. The General Description MM74HC4049 is pin and functionally compatible to the The MM74HC4049 and the MM74HC4050 utilize CD4049BC and the MM74HC4050 is compatible to the advanced silicon-gate CMOS technology, and have a mod- CD4050BC ified input protection structure that enables these parts to be used as logic level translators which will convert high Features level logic to a low level logic while operating from the low logic supply. For example, 015V CMOS logic can be con- Typical propagation delay: 8 ns verted to 05V logic when using a 5V supply. The modified Wide power supply range: 2V6V input protection has no diode connected to V , thus allow- CC Low quiescent supply current: 20 A maximum (74HC) ing the input voltage to exceed the supply. The lower zener Fanout of 10 LS-TTL loads diode protects the input from both positive and negative static voltages. In addition each part can be used as a sim- Ordering Code: Order Number Package Number Package Description MM74HC4049M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC4049SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC4049MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide MM74HC4049N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide MM74HC4050M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC4050SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC4050MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide MM74HC4050N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagrams MM74HC4049 MM74HC4050 1999 Fairchild Semiconductor Corporation DS005214 www.fairchildsemi.comAbsolute Maximum Ratings(Note 1) Recommended Operating (Note 2) Conditions Supply Voltage (V ) - 0.5 to +7.0V CC Min Max Units DC Input Voltage (V ) - 1.5 to +18V IN Supply Voltage (V)26V CC DC Output Voltage (V ) - 0.5 to V +0.5V OUT CC DC Input Voltage 0 15 V Clamp Diode Current (I , I ) - 20 mA ZK OK (V ) IN DC Output Current, per pin (I ) 25 mA OUT DC Output Voltage 0 V V CC DC V or GND Current, per pin (I ) 50 mA CC CC (V ) OUT Storage Temperature Range (T ) - 65C to +150C STG Operating Temperature Range (T ) - 40 +85 C A Power Dissipation (P ) D Input Rise or Fall Times (Note 3) 600 mW (t , t) V = 2.0V 1000 ns r f CC S.O. Package only 500 mW V = 4.5V 500 ns CC Lead Temperature (T ) L V = 6.0V 400 ns CC (Soldering 10 seconds) 260C Note 1: Absolute Maximum Ratings are those values beyond which dam- age to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating plastic N package: - 12 mW/C from 65C to 85C. DC Electrical Characteristics (Note 4) T = 25CT = - 40C to 85CT = - 55C to 125C A A A Symbol Parameter Conditions V Units CC Typ Guaranteed Limits V Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 V IH Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V V Maximum LOW Level Input 2.0V 0.5 0.5 0.5 V IL Voltage 4.5V1.351.351.35V 6.0V1.81.81.8V V Minimum HIGH Level V = V or V OH IN IH IL Output Voltage I 20 A 2.0V 2.0 1.9 1.9 1.9 V OUT 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V V = V or V IN IH IL I 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V OUT I 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V OUT V Maximum LOW Level V = V or V OL IN IH IL Output Voltage I 20 A 2.0V 0 0.1 0.1 0.1 V OUT 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V V = V or V IN IH IL I 4 mA 4.5V 0.2 0.26 0.33 0.4 V OUT I 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V OUT I Maximum Input Current V = V or GND 6.0V 0.1 1.0 1.0 A IN IN CC V = 15V 2.0V 0.5 5 5 A IN I Maximum Quiescent Supply V = V or GND 6.0V 2.0 20 40 A CC IN CC Current I = 0 A OUT Note 4: For a power supply of 5V 10% the worst case output voltages (V and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when OH OL designing with this supply. Worst case V and V occur at V = 5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage cur- IH IL CC IH rent (I , I , I ) occur for CMOS at the higher voltage and so the 6.0V values should be used. IN CC OZ www.fairchildsemi.com 2 MM74HC4049 MM74HC4050