MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer September 1983 Revised May 2005 MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer General Description Features The MM74HC540 and MM74HC541 3-STATE buffers uti- Typical propagation delay: 12 ns lize advanced silicon-gate CMOS technology. They pos- 3-STATE outputs for connection to system buses sess high drive current outputs which enable high speed Wide power supply range: 26V operation even when driving large bus capacitances. Low quiescent current: 80 PA maximum (74HC Series) These circuits achieve speeds comparable to low power Schottky devices, while retaining the advantage of CMOS Output current: 6 mA circuitry, i.e., high noise immunity, and low power consump- tion. Both devices have a fanout of 15 LS-TTL equivalent inputs. The MM74HC540 is an inverting buffer and the MM74HC541 is a non-inverting buffer. The 3-STATE con- trol gate operates as a two-input NOR such that if either G1 or G2 are HIGH, all eight outputs are in the high-imped- ance state. In order to enhance PC board layout, the MM74HC540 and MM74HC541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected from damage due to static discharge by diodes to V and CC ground. Ordering Code: Order Number Package Number Package Description MM74HC540WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HC540SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC540MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC540N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide MM74HC541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HC541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC, SOP and TSSOP Top View MM74HC541 Top View MM74HC540 2005 Fairchild Semiconductor Corporation DS005341 www.fairchildsemi.comAbsolute Maximum Ratings(Note 1) Recommended Operating (Note 2) Conditions Supply Voltage (V ) 0.5 to 7.0V CC Min Max Units DC Input Voltage (V ) 1.5 to V 1.5V IN CC Supply Voltage (V)26V CC DC Output Voltage (V ) 0.5 to V 0.5V OUT CC DC Input or Output Voltage Clamp Diode Current (I ) r20 mA CD (V , V)0V V IN OUT CC DC Output Current, per pin (I ) r35 mA OUT Operating Temperature Range (T ) 40 85 qC A DC V or GND Current, CC Input Rise or Fall Times per pin (I ) r70 mA CC (t , t) V 2.0V 1000 ns r f CC Storage Temperature Range (T ) 65qC to 150 qC STG V 4.5V 500 ns CC Power Dissipation (P ) D V 6.0V 400 ns CC (Note 3) 600 mW Note 1: Absolute Maximum Ratings are those values beyond which dam- age to the device may occur. S.O. Package only 500 mW Note 2: Unless otherwise specified all voltages are referenced to ground. Lead Temperature (T ) L Note 3: Power Dissipation temperature derating plastic N package: (Soldering 10 seconds) 260 qC 12 mW/qC from 65 qC to 85 qC. DC Electrical Characteristics (Note 4) T 25qCT 40 to 85qCT 55 to 125qC A A A V Symbol Parameter Conditions Units CC Typ Guaranteed Limits V Minimum HIGH Level 2.0V 1.5 1.5 1.5 V IH Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V V Maximum LOW Level 2.0V 0.5 0.5 0.5 V IL Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V V Minimum HIGH Level V V or V OH IN IH IL Output Voltage I d 20 PA 2.0V 2.0 1.9 1.9 1.9 V OUT 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V V V or V IN IH IL I d 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V OUT I d 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V OUT V Maximum LOW Level V V or V OL IN IH IL Output Voltage I d 20 PA 2.0V 0 0.1 0.1 0.1 V OUT 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V V V or V IN IH IL I d 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V OUT I d 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V OUT I Maximum Input V V or GND 6.0V r0.1 r1.0 r1.0 PA IN IN CC Current I Maximum 3-STATE V V or V , G V 6.0V r0.5 r5 r10 PA OZ IN IH IL IH Output Leakage V V or GND OUT CC Current I Maximum Quiescent V V or GND 6.0V 8.0 80 160 PA CC IN CC Supply Current I 0 PA OUT Note 4: For a power supply of 5V r10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when OH OL designing with this supply. Worst case V and V occur at V 5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage cur- IH IL CC IH rent (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used. IN CC OZ www.fairchildsemi.com 2 MM74HC540 MM74HC541