MM74HCT138 3-to-8 Line Decoder February 1984 Revised February 1999 MM74HCT138 3-to-8 Line Decoder the 74LS138. All inputs are protected from damage due to General Description static discharge by diodes to V and ground. CC The MM74HCT138 decoder utilizes advanced silicon-gate MM74HCT devices are intended to interface between TTL CMOS technology, and are well suited to memory address and NMOS components and standard CMOS devices. decoding or data routing applications. Both circuits feature These parts are also plug-in replacements for LS-TTL high noise immunity and low power consumption usually devices and can be used to reduce power consumption in associated with CMOS circuitry, yet have speeds compara- existing designs. ble to low power Schottky TTL logic. The MM74HCT138 have 3 binary select inputs (A, B, and Features C). If the device is enabled these inputs determine which one of the eight normally HIGH outputs will go LOW. Two TTL input compatible active LOW and one active HIGH enables (G1, G2A and Typical propagation delay: 20 ns G2B) are provided to ease the cascading decoders. Low quiescent current: 80 A maximum (74HCT Series) The decoders output can drive 10 low power Schottky TTL Low input current: 1 A maximum equivalent loads and are functionally and pin equivalent to Fanout of 10 LS-TTL loads Ordering Code: Order Number Package Number Package Description MM74HCT138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HCT138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP 1999 Fairchild Semiconductor Corporation DS005362.prf www.fairchildsemi.comTruth Table Inputs Outputs Enable Select G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 (Note 1) X H X X X HHHHHHHH L X X X X HHHHHHHH H L LLLL HHHHHHH H L L L HH L HHHHHH H L L H L H H L HHHHH H L L HHHHH L HHHH H L H L L HHHH L HHH H L H L HHHHHH L H H H L HH L HHHHHH L H H L HHHHHHHHHH L H = HIGH Level L = LOW Level X = Dont Care Note 1: G2 = G2A + G2B Logic Diagram www.fairchildsemi.com 2 MM74HCT138