MM74HC251 8-Channel 3-STATE Multiplexer September 1983 Revised February 1999 MM74HC251 8-Channel 3-STATE Multiplexer to the Y and W outputs. The 74HC logic family is speed, General Description function, as well as pinout compatible with the standard The MM74HC251 8-channel digital multiplexer with 3- 74LS logic family. All inputs are protected from damage STATE outputs utilizes advanced silicon-gate CMOS tech- due to static discharge by internal diode clamps to V and CC nology. Along with the high noise immunity and low power ground. consumption of standard CMOS integrated circuits, it pos- sesses the ability to drive 10 LS-TTL loads. The large out- Features put drive capability and 3-STATE feature make this part ideally suited for interfacing with bus lines in a bus oriented Typical propagation delay system. Data select to Y: 26 ns This multiplexer features both true (Y) and complement Wide supply range: 26V (W) outputs as well as a STROBE input. The STROBE Low power supply quiescent current: must be at a low logic level to enable this device. When the 80 A maximum (74HC) STROBE input is HIGH, both outputs are in the high 3-STATE outputs for interface to bus oriented impedance state. When enabled, address information on the data select inputs determines which data input is routed systems Ordering Code: Order Number Package Number Package Description MM74HC251M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow MM74HC251SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC251MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC251N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View 1999 Fairchild Semiconductor Corporation DS005328.prf www.fairchildsemi.comTruth Table Inputs Outputs Select Strobe YW CBA S XX X H Z Z L L L L D0 D0 L L H L D1 D1 L H L L D2 D2 L H H L D3 D3 H L L L D4 D4 H L H L D5 D5 H H L L D6 D6 HHH L D7 D7 H = HIGH Logic Level, L = LOW Logic Level X = Irrelevant, Z = High Impedance (off) D0, D1 . D7 = The level of the respective D input Logic Diagram www.fairchildsemi.com 2 MM74HC251