2.5 V/3.3 V Quad Differential Driver/Receiver NB100LVEP17 Description The NB100LVEP17 is a 4-bit differential line receiver. The design www.onsemi.com incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V 24 1 BB BB and V via a 0.01 F capacitor and limit current sourcing or sinking CC 24 PIN QFN TSSOP20 to 0.5 mA. When not used, V should be left open. BB DT SUFFIX MN SUFFIX Inputs of unused gates can be left open and will not affect the CASE 948E CASE 485L operation of the rest of the device. Features MARKING DIAGRAMS* Maximum Input Clock Frequency > 2.5 GHz Typical Maximum Input Data Rate > 2.5 Gb/s Typical 24 250 ps Typical Propagation Delay 1 N100 N100 Low Profile QFN Package VP17 VP17 ALYW ALYW PECL Mode Operating Range: V = 2.375 V to 3.8 V CC with V = 0 V EE NECL Mode Operating Range: V = 0 V CC with V = 2.375 V to 3.8 V EE A = Assembly Location Q Output Will Default LOW with Inputs Open or at V EE L = Wafer Lot Y = Year V Output BB W = Work Week These Devices are PbFree, Halogen Free and RoHS Compliant = PbFree Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping 2500 / NB100LVEP17DTR2G TSSOP20 Tape & Reel (PbFree) 92 Units / Tube NB100LVEP17MNG QFN24 (PbFree) 3000 / NB100LVEP17MNR2G QFN24 Tape & Reel (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifica- tion Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: May, 2021 Rev. 9 NB100LVEP17/DNB100LVEP17 D0 Q0 R1 R2 D0 Q0 R1 D1 Q1 R1 R2 D1 Q1 R1 D2 Q2 R1 R2 D2 Q2 R1 V CC V EE D3 Q3 R1 R2 V D3 Q3 BB R1 Figure 1. Logic Diagram Table 1. PIN DESCRIPTION Pin Default TSSOP QFN State Name I/O Description 1,20 13,18,21, V Positive Supply Voltage. All V Pins Must be Externally Connected CC CC 22,23 to Power Supply to Guarantee Proper Operation. 11 10 V Negative Supply Voltage. All V Pins Must be Externally Con- EE EE nected to Power Supply to Guarantee Proper Operation. 10 9 V ECL Reference Voltage Output. BB 2,4,6,8 1,3,5,7 D 0:3 ECL Input Low Noninverted Differential Inputs 0:3 . Internal 75 k to V . EE 3,5,7,9 2,4,6,8 D 0:3 ECL Input High Inverted Differential Inputs 0:3 . Internal 75 k to V and 37 k to EE V . CC 19,17,15,13 12,15,17,2 Q 0:3 ECL Output Noninverted Differential Outputs 0:3 . Typically Terminated with 0 50 to V = V 2 V. TT CC 18,16,14,12 11,14,16,1 Q 0:3 ECL Output Inverted Differential Outputs 0:3 . Typically Terminated with 50 to 9 V = V 2 V. TT CC N/A 24 NC No Connect. The NC Pin is Electrically Connected to the Die and MUST BE Left Open. N/A EP Exposed Pad. (Note 1) 1. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally conductive expose pad CC EE on the package bottom (see case drawing) must be attached to a heatsinking conduit. www.onsemi.com 2