2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator NB100LVEP91 www.onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential 20 LVNECL output signals (2.5 V/3.3 V). 1 24 1 To accomplish the level translation the LVEP91 requires three power rails. The V pins should be connected to the positive power CC SOIC20 WB QFN24 supply, and the V pin should be connected to the negative power DW SUFFIX MN SUFFIX EE CASE 751D05 CASE 485L01 supply. The GND pins are connected to the system ground plane. Both V and V should be bypassed to ground via 0.01 F capacitors. EE CC Under open input conditions, the D input will be biased at V /2 CC and the D input will be pulled to GND. These conditions will force the MARKING DIAGRAMS* Q outputs to a low state, and Q outputs to a high state, which will 20 24 ensure stability. 1 The V pin, an internally generated voltage supply, is available to BB N100 NB100LVEP91 VP91 this device only. For single-ended input conditions, the unused ALYW AWLYYWWG differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB 1 and V via a 0.01 F capacitor and limit current sourcing or sinking CC to 0.5 mA. When not used, V should be left open. BB A = Assembly Location WL, L = Wafer Lot Features YY, Y = Year Maximum Input Clock Frequency > 2.0 GHz Typical WW, W = Work Week G or = Pb-Free Package Maximum Input Data Rate > 2.0 Gb/s Typical (Note: Microdot may be in either location) 500 ps Typical Propagation Delay Operating Range: *For additional marking information, refer to Application Note AND8002/D. V = 2.375 V to 3.8 V V = 2.375 V to 3.8 V GND = 0 V CC EE Q Output will Default LOW with Inputs Open or at GND These Devices are Pb-Free, Halogen Free and are RoHS Compliant ORDERING INFORMATION Device Package Shipping NB100LVEP91DWG SOIC20 WB 38 Units/Tube (Pb-Free) NB100LVEP91DWR2G SOIC20 WB 1000/Tape & Reel (Pb-Free) NB100LVEP91MNG 92 Units/Tube QFN24 (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please re- fer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: May, 2021 Rev. 21 NB100LVEP91/DNB100LVEP91 Positive Level NECL Output Input D0 Q0 R1 R2 D0 Q0 R1 D1 Q1 R1 R2 V CC D1 Q1 V BB R1 GND D2 Q2 R1 V EE R2 D2 Q2 R1 Figure 1. Logic Diagram Table 1. PIN DESCRIPTION Pin Default SOIC QFN Name I/O State Description 1, 20 3, 4, 12 V Positive Supply Voltage. All V Pins must be Externally CC CC Connected to Power Supply to Guarantee Proper Operation. 10 15, 16 V Negative Supply Voltage. All V Pins must be Externally EE EE Connected to Power Supply to Guarantee Proper Operation. 14, 17 19, 20, GND Ground. 23, 24 4, 7 7, 11 V ECL Reference Voltage Output BB 2, 5, 8 5, 8, 13 D 0:2 LVPECL, LVDS, LVTTL, Low Non-inverted Differential Inputs 0:2 . Internal 75 k to GND. LVCMOS, CML, HSTL Input 3, 6, 9 6, 9, 14 D 0:2 LVPECL, LVDS, High Inverted Differential Inputs 0:2 . Internal 75 k to GND and LVTTL,LVCMOS, CML, 75 k to V . When Inputs are Left Open They Default to CC HSTL Input (V GND) / 2. CC 19,16,13 2, 22, 18 Q 0:2 LVNECL Output Non-inverted Differential Outputs 0:2 . Typically Terminated with 50 to V = V 2 V TT CC 18,15,12 1, 21, 17 Q 0:2 LVNECL Output Inverted Differential Outputs 0:2 . Typically Terminated with 50 to V = V 2 V TT CC 11 10 NC No Connect. The NC Pin is NOT Electrically Connected to the Die and may Safely be Connected to Any Voltage from V to V . EE CC N/A EP Exposed Pad. (Note 1) 1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit and may only be electrically connected to V (not GND). EE www.onsemi.com 2