3.3 V Zero Delay Clock Buffer NB2304A The NB2304A is a versatile, 3.3 V zero delay buffer designed to distribute highspeed clocks in PC, workstation, datacom, telecom and other highperformance applications. It is available in an 8 pin www.onsemi.com package. The part has an onchip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The inputtooutput propagation delay is guaranteed to be less than 8 250 ps, and the output tooutput skew is guaranteed to be less than 1 200 ps. SOIC8 The NB2304A has two Banks of two outputs each. Multiple D SUFFIX NB2304A devices can accept the same input clock and distribute it. In CASE 751 this case, the skew between the outputs of the two devices is guaranteed to be less than 500 ps. The NB2304A is available in two different configurations (Refer to MARKING DIAGRAM NB2304A Configurations Table). The NB2304AI1 is the base part, 8 where the output frequencies equal the reference if there is no counter 4lx in the feedback path. The NB2304AI2 allows the user to obtain REF, ALYW 1/2 X and 2X frequencies on each output Bank. The exact configuration and output frequencies depend on which output drives 1 the feedback pin. 4lx = Specific Device Code Features x = 1 or 2 Zero Input Output Propagation Delay, Adjustable by Capacitive A = Assembly Location L = Wafer Lot Load on FBK Input Y = Year Multiple Configurations Refer to NB2304A Configurations Table W = Work Week Input Frequency Range: 15 MHz to 133 MHz = PbFree Package *For additional marking information, refer to Multiple LowSkew Outputs Application Note AND8002/D. OutputOutput Skew < 200 ps DeviceDevice Skew < 500 ps ORDERING INFORMATION Two Banks of Four Outputs See detailed ordering and shipping information in the package Less than 200 ps CycletoCycle Jitter (1) dimensions section on page 6 of this data sheet. Available in Space Saving, 8 pin 150 mil SOIC Package 3.3 V Operation Advanced 0.35 CMOS Technology Guaranteed Across Commercial and Industrial Temperature Ranges These Devices are PbFree, Halogen Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2010 1 Publication Order Number: May, 2021 Rev. 10 NB2304A/DNB2304A FBK CLKA1 PLL REF CLKA2 2 Extra Divider (2) CLKB1 CLKB2 Figure 1. Basic Block Diagram (see Figures 10 and 11 for device specific Block Diagrams) Table 1. CONFIGURATIONS Device Feedback From Bank A Frequency Bank B Frequency NB2304AI1 Bank A or Bank B Reference Reference NB2304AI2 Bank A Reference Reference 2 NB2304AI2 Bank B 2 X Reference Reference Table 2. PIN DESCRIPTION REF 1 8 FBK Pin Pin Name Description 1 REF (Note 1) Input reference frequency, 5 V 2 CLKA1 7 V DD tolerant input. NB2304A 2 CLKA1 (Note 2) Buffered clock output, Bank A. CLKA2 3 6 CLKB2 3 CLKA2 (Note 2) Buffered clock output, Bank A. 4 GND Ground. GND 4 5 CLKB1 5 CLKB1 (Note 2) Buffered clock output, Bank B. 6 CLKB2 (Note 2) Buffered clock output, Bank B. Figure 2. Pin Configuration 7 V 3.3 V supply. DD 8 FBK PLL feedback input. 1. Weak pulldown. 2. Weak pulldown on all outputs. www.onsemi.com 2