NB2308AI3DR2G ON Semiconductor

NB2308A 3.3 V Zero Delay Clock Buffer The NB2308A is a versatile, 3.3 V zero delay buffer designed to distribute high--speed clocks. It is available in a 16 pin package. The part has an on--chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin, NB2308A FBK 2 PLL REF 2 CLKA1 ExtraDivider(--3, --4) MUX CLKA2 Extra Divider (--5H) CLKA3 S2 CLKA4 SELECTINPUT DECODING S1 2 CLKB1 ExtraDivider(--2, --3) CLKB2 CLKB3 CLKB4 Figure1.BlockDiagram (see Figures 11, 12, 13, 14 and 15 for device specific Block Diagrams) Table1.CONFIGURATIONS Device FeedbackFrom BankAFrequency BankBFrequency NB2308AI1 Bank A or Bank B Reference Reference NB2308AI1H Bank A or Bank B Reference Reference NB2308AI2 Bank A Reference Reference 2 NB2308AI2 Bank B 2 X Reference Reference NB2308AI3 Bank A 2 X Reference Reference or Reference (Note 1) NB2308AI3 Bank B 4 X Reference 2 X Reference NB2308AI4 Bank A or Bank B 2 X Reference 2 X Reference NB2308AI5H Bank A or Bank B Reference 2 Reference 2 1. Output phase is indeterminant (0 or 180 from input clock). If phase integrity is required, use the NB2308AI2. Table2.SELECTINPUTDECODING S2 S1 ClockA1 -- A4 ClockB1 -- B4 OutputSource PLLShutDown 0 0 Three--state Three--state PLL Y 0 1 Driven Three--state PLL N 1 0 Driven (Note 2) Driven Reference Y 1 1 Driven Driven PLL N 2. Outputs inverted on 2308--2 and 2308--3 in bypass mode, S2 =1 and S1 =0.