3.3 V Zero Delay Clock Buffer NB2309A The NB2309A is a versatile, 3.3 V zero delay buffer designed to distribute highspeed clocks. It accepts one reference input and drives out nine lowskew clocks. It is available in a 16 pin package. www.onsemi.com The 1H version of the NB2309A operates at up to 133 MHz, and has higher drive than the 1 devices. All parts have onchip PLLs that MARKING lock to an input clock on the REF pin. The PLL feedback is onchip DIAGRAMS* and is obtained from the CLKOUT pad. The NB2309A has two banks of four outputs each, which can be 16 controlled by the Select inputs as shown in the Select Input Decoding 16 XXXXXXXXG Table. If all the output clocks are not required, Bank B can be 1 AWLYWW threestated. The select inputs also allow the input clock to be directly SOIC16 applied to the outputs for chip and system testing purposes. 1 D SUFFIX Multiple NB2309A devices can accept the same input clock and CASE 751B distribute it. In this case the skew between the outputs of the two 16 devices is guaranteed to be less than 700 ps. XXXX 16 All outputs have less than 200 ps of cycletocycle jitter. The input XXXX ALYW and output propagation delay is guaranteed to be less than 350 ps, and 1 the output to output skew is guaranteed to be less than 250 ps. TSSOP16 1 The NB2309A is available in two different configurations, as shown DT SUFFIX CASE 948F in the ordering information table. The NB2309A1 is the base part. The NB2309AI1H is the high drive version of the 1 and its rise and fall XXXX = Device Code times are much faster than 1 part. A = Assembly Location WL, L = Wafer Lot Features Y = Year 15 MHz to 133 MHz Operating Range, Compatible with CPU and W, WW = Work Week PCI Bus Frequencies G or = PbFree Package (Note: Microdot may be in either location) Zero Input Output Propagation Delay Multiple LowSkew Outputs *For additional marking information, refer to Application Note AND8002/D. OutputOutput Skew Less than 250 ps DeviceDevice Skew Less than 700 ps ORDERING INFORMATION One Input Drives 9 Outputs, Grouped as 4 + 4 + 1 See detailed ordering, marking and shipping information in the Less than 200 ps CycletoCycle Jitter is Compatible with Pentium package dimensions section on page 7 of this data sheet. Based Systems Test Mode to Bypass PLL Accepts Spread Spectrum Clock at the Input Available in 16 Pin, 150 mil SOIC and 4.4 mm TSSOP 3.3 V Operation, Advanced 0.35 CMOS Technology Guaranteed Across Commercial and Industrial Temperature Ranges These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: May, 2021 Rev. 12 NB2309A/DNB2309A PLL CLKOUT MUX REF CLKA1 CLKA2 CLKA3 CLKA4 S2 SELECT INPUT DECODING CLKB1 S1 CLKB2 CLKB3 CLKB4 Figure 1. Block Diagram Table 1. SELECT INPUT DECODING CLKOUT PLL (Note 1) ShutDown S2 S1 Clock A1 A4 Clock B1 B4 Output Source 0 0 Threestate Threestate Driven PLL N 0 1 Driven Threestate Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the output. www.onsemi.com 2