NB3F8L3010C
3.3V / 2.5V / 1.8V / 1.5V
3:1:10 LVCMOS Fanout Buffer
Description
The NB3F8L3010C is a 3:1:10 Clock / Data fanout buffer operating
on a 3.3 V / 2.5 V Core V and two flexible 3.3 V / 2.5 V / 1.8 V /
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DD
1.5 V VDDO supplies which must be equal or less than V .
n DD
A Mux selects between a Crystal input, or either of two
differential/SE Clock / Data inputs. Differential Inputs accept
MARKING
LVPECL, LVDS, HCSL, or SSTL and SingleEnded levels. The
DIAGRAM
MUX control lines, SEL0 and SEL1, select CLK0/CLK0,
1
CLK1/CLK1, or Crystal input pins per Table 3. The Crystal input is
NB3F8L
1 32
disabled when a Clock input is selected. Output enable pin, OE,
3010C
QFN32
synchronously forces a High Impedance state (HZ) when Low per
AWLYYWWG
G SUFFIX
Table 4.
CASE 488AM
Outputs consist of 10 singleended LVCMOS outputs.
A = Assembly Location
Features
WL = Wafer Lot
Ten CMOS / LVTTL Outputs up to 200 MHz
YY = Year
WW = Work Week
Differential Inputs Accept LVPECL, LVDS, HCSL, or SSTL
G = PbFree Package
Crystal Oscillator Interface
Crystal Input Frequency Range: 10 MHz to 50 MHz
ORDERING INFORMATION
Output Skew: 10 ps Typical
See detailed ordering and shipping information page 12 of this
data sheet.
Additive RMS Phase Jitter @ 125 MHz, (12 kHz 20 MHz): 0.03 ps
(Typical)
Synchronous Output Enable
Output Defined Level When Input is Floating
Power Supply Modes:
Single 3.3 V
Single 2.5 V
Mixed 3.3 V 5% Core/2.5 V 5% Output Operating Supply
Mixed 3.3 V 5% Core/1.8 V 0.2 V Output Operating Supply
Mixed 3.3 V 5% Core/1.5 V 0.15 V Output Operating Supply
Mixed 2.5 V 5% Core/ 1.8 V 0.2 V Output Operating Supply
Mixed 2.5 V 5% Core /1.5 V 0.15 V Output Operating Supply
Two Separate Output Bank Power Supplies
Industrial temp. range -40C to 85C
These are PbFree Devices
Applications
Clock Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure
End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
May, 2016 Rev. 7 NB3F8L3010C/DNB3F8L3010C
BANK A
VDD Q0
VDDOA
VDDOB
Q1
GND
SEL0
Q2
SEL1
Q3
CLK0
CLK0
Q4
CLK1
CLK1
BANK B
XTAL_IN
OSC
XTAL_OUT
Q5
Q6
Q7
Q8
Q9
OE SYNC
Figure 1. Simplified Logic Diagram
Exposed Pad (EP)
Q0 Q9
24
1
VDDOA VDDOB
2 23
Q1 Q8
3 22
GND
21 GND
4
NB3F8L3010C
Q2 Q7
5 20
VDDOA
6 19 VDDOB
Q3
Q6
7 18
Q4
8 17 Q5
Figure 2. Pinout Configuration (Top View)
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2
32 GND
9
GND
31 OE
10
VDD
11 30
XTAL_IN SEL0
29 SEL1
XTAL_OUT 12
CLK1
CLK0 13 28
14 27
CLK0 CLK1
26
GND 15 GND
GND 16 25 GND