NB3H60113G 3.3 V / 2.5 V Programmable OmniClock Generator with Single Ended (LVCMOS/LVTTL) and Differential (LVPECL/LVDS/ HCSL/CML) www.onsemi.com Outputs The NB3H60113G, which is a member of the OmniClock family, is a onetime programmable (OTP), low power PLLbased clock generator that supports any output frequency from 8 kHz to 200 MHz. The device accepts fundamental mode parallel resonant crystal or a WDFN8 single ended (LVCMOS/LVTTL) reference clock as input. It CASE 511AT generates either three single ended (LVCMOS/LVTTL) outputs, or one single ended output and one differential MARKING DIAGRAM (LVPECL/LVDS/HCSL/CML) output. The output signals can be 1 modulated using the spread spectrum feature of the PLL H0M (programmable spread spectrum type, deviation and rate) for applications demanding low electromagnetic interference (EMI). H0 = Specific Device Code Using the PLL bypass mode, it is possible to get a copy of the input M = Date Code clock on any or all of the outputs. The device can be powered down = PbFree Device using the Power Down pin (PD ). It is possible to program the internal (Note: Microdot may be in either location) input crystal load capacitance and the output drive current provided by the device. The device also has automatic gain control (crystal power limiting) circuitry which avoids the device overdriving the external ORDERING INFORMATION See detailed ordering and shipping information on page 21 of crystal. this data sheet. Features Member of the OmniClock Family of Programmable Clock Generators Operating Power Supply: 3.3 V 10%, 2.5 V 10% I/O Standards Inputs: LVCMOS/LVTTL, Fundamental Mode Power Saving mode through Power Down Pin Crystal Programmable PLL Bypass Mode Outputs: LVCMOS/LVTTL Programmable Output Inversion Outputs: LVPECL, LVDS, CML and HCSL Programming and Evaluation Kit for Field 3 Programmable Single Ended (LVCMOS/LVTTL) Programming and Quick Evaluation Outputs from 8 kHz to 200 MHz Temperature Range 40C to 85C 1 Programmable Differential Clock Output up to Packaged in 8Pin WDFN 200 MHz These are PbFree Devices Input Frequency Range Crystal: 3 MHz to 50 MHz Typical Applications Reference Clock: 3 MHz to 200 MHz eBooks and Media Players Configurable Spread Spectrum Frequency Modulation Smart Wearables, Portable Medical and Industrial Parameters (Type, Deviation, Rate) Equipment Programmable Internal Crystal Load Capacitors Set Top Boxes, Printers, Digital Cameras and Programmable Output Drive Current for Single Ended Camcorders Outputs Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: January, 2016 Rev. 2 NB3H60113G/DNB3H60113G BLOCK DIAGRAM PD VDD Crystal/Clock Control Output control Configuration Memory Frequency CMOS/ Output and SS CLK0 Diff Divider buffer PLL Block XIN/CLKIN Clock Buffer/ Crystal Phase Charge VCO CMOS / Crystal Output Oscillator and Detector Pump Diff CLK1 AGC Divider buffer XOUT Feedback Output CMOS CLK2 Divider Divider buffer PLL Bypass Mode GND Notes: 1. CLK0 and CLK1 can be configured to be one of LVPECL, LVDS, HCSL or CML output, or two singleended LVCMOS/ LVTTL outputs. 2. Dotted lines are the programmable control signals to internal IC blocks. 3. PD has internal pull down resistor. Figure 1. Simplified Block Diagram PIN FUNCTION DESCRIPTION XIN/CLKIN 1 8 CLK2 2 7 XOUT VDD NB3H60113G 3 6 CLK1 PD 4 5 GND CLK0 Figure 2. Pin Connections (Top View) WDFN8 www.onsemi.com 2