NB3H73113G 3.3 V / 2.5 V Programmable OmniClock Generator with 2 I C / SMBus Interface The NB3H73113G, which is a member of the OmniClock family, is a onetime programmable (OTP), low power PLLbased clock www.onsemi.com generator that supports any output frequency from 8 kHz to 200 MHz. The device accepts fundamental mode parallel resonant crystal or a MARKING DIAGRAM single ended (LVCMOS/LVTTL) reference clock as input. It generates either three single ended (LVCMOS/LVTTL) outputs, or 3H731 1 one single ended output and one differential 13Gxx (LVPECL/LVDS/HCSL/CML) output. The output signals can be QFN16 ALYW CASE 485AE modulated using the spread spectrum feature of the PLL (programmable spread spectrum type, deviation and rate) for applications demanding low electromagnetic interference (EMI). 3H73113G = Specific Device Code Individual output enable pins OE 2:0 are available to enable/disable xx = Specific Program Code (Default 00 for Unprogrammed Part) the outputs. Individual output voltage pins VDDO 2:0 are available A = Assembly Location to independently set the output voltage of each output. The device L = Wafer Lot 2 supports SMBus / I C interface with SCLK and SDATA signals. Using Y = Year the standard protocol, data in the device registers can be modified to W = Work Week support different configurations. Using the PLL bypass mode, it is = PbFree Package possible to get a copy of the input clock on any or all of the outputs. (Note: Microdot may be in either location) The device can be powered down using the Power Down pin (PD ). It is possible to program the internal input crystal load capacitance and ORDERING INFORMATION the output drive current provided by the device. The device also has See detailed ordering and shipping information on page 23 of automatic gain control (crystal power limiting) circuitry which avoids this data sheet. the device overdriving the external crystal. Features Member of the OmniClock Family of Programmable Independent Output Voltage Pins Clock Generators Programmable Internal Crystal Load Capacitors Operating Power Supply: 3.3 V 10%, 2.5 V 10% Programmable Output Drive Current for Single Ended 2 Supports SMBus / I C Interface Outputs I/O Standards Power Saving Mode through Power Down Pin Inputs: LVCMOS/LVTTL, Fundamental Mode Programmable PLL Bypass Mode Crystal Programmable Output Inversion Outputs: 1.8 V to 3.3 V LVCMOS/LVTTL Programming and Evaluation Kit Available for Field Outputs: LVPECL, LVDS, HCSL and CML Programming and Quick Evaluation 3 Programmable Single Ended (LVCMOS/LVTTL) Temperature Range 40C to 85C Outputs from 8 kHz to 200 MHz Packaged in 16pin QFN 1 Programmable Differential Clock Output up to These are PbFree Devices 200 MHz Input Frequency Range Typical Applications Crystal: 3 MHz to 50 MHz eBooks and Media Players Reference Clock: 3 MHz to 200 MHz Smart Wearables, Smart Phones, Portable Medical and Configurable Spread Spectrum Frequency Modulation Industrial Equipment Parameters (Type, Deviation, Rate) Set Top Boxes, Printers, Digital Cameras and Individual Output Enable Pins Camcorders Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: March, 2017 Rev. 0 NB3H73113G/DNB3H73113G BLOCK DIAGRAM VDD PD SCLK SDATA Input Decoder Output control Configuration Crystal/Clock Control Memory VDDO0 Frequency CMOS/ Output and SS DIFF CLK0 Divider buffer PLL Block XIN/ CLKIN OE0 Clock Buffer/ Crystal Phase Charge VDDO1 VCO Oscillator And Detector Pump Crystal CMOS/ AGC XOUT Output CLK1 DIFF Divider buffer Feedback OE1 Divider VDDO2 Output CMOS CLK2 Divider buffer PLL Bypass Mode OE2 GND GNDO Notes: 1. CLK0 and CLK1 can be configured to be one LVPECL, LVDS, HCSL or CML output, or two single ended LVCMOS/LVTTL outputs. 2. Dotted lines are the programmable control signals to internal IC blocks. 3. OE 2:0 , SCLK and SDATA have internal pull up resistors. PD has internal pull down resistor. Figure 1. Simplified Block Diagram PIN FUNCTION DESCRIPTION 16 15 14 13 NB3H73113G XIN/CLKIN 1 12 VDD XOUT 2 11 VDDO1 GNDO (EPAD) PD 3 10 CLK1 GND 4 9 CLK0 5 6 7 8 Figure 2. Pin Connections (Top View) QFN16 (with EPAD) www.onsemi.com 2 OE0 SCLK OE1 SDATA OE2 VDDO2 VDDO0 CLK2