3.3V / 2.5V / 1.8V / 1.5V 2:1:5 LVCMOS Fanout Buffer NB3F8L3005C Description The NB3F8L3005C is a 2:1:5 Clock / Data fanout buffer operating on a 3.3 V / 2.5 V Core V and two flexible 3.3 V / 2.5 V / 1.8 V / www.onsemi.com DD 1.5 V VDDO supplies which must be equal or less than V . x DD A Mux selects between a Crystal input, or a differential/SE Clock / Data inputs. Differential Inputs accept LVPECL, LVDS, HCSL, or MARKING SSTL and Single Ended levels. The MUX control line, SEL selects DIAGRAM CLK/CLK, or Crystal input pins per Table 3. The Crystal input is 1 disabled when a Clock input is selected. Output enable pin, OE, NB3F8L 3005C synchronously forces a High Impedance state (HiZ) when Low per ALYW QFN24 Table 4. G SUFFIX Outputs consist of five singleended LVCMOS outputs. CASE 485DJ Features A = Assembly Location L = Wafer Lot Five LVCMOS / LVTTL Outputs up to 200 MHz Y = Year Differential Inputs Accept LVPECL, LVDS, HCSL, SSTL, or W = Work Week LVCMOS/LVTTL = PbFree Package Crystal Interface (Note: Microdot may be in either location) Crystal Input Frequency Range: 10 MHz to 50 MHz Output Skew: 10 ps Typical ORDERING INFORMATION Additive RMS Phase Jitter 156.25 MHz, (12 kHz 20 MHz): See detailed ordering and shipping information on page 12 of 0.03 ps (Typical) this data sheet. Synchronous Output Enable Output Defined Level When Input is Floating Power Supply Modes: Single 3.3 V 5% Single 2.5 V 5% Mixed 3.3 V 5% Core/2.5 V 5% Output Operating Supply Mixed 3.3 V 5% Core/1.8 V 0.2 V Output Operating Supply Mixed 3.3 V 5% Core/1.5 V 0.15 V Output Operating Supply Mixed 2.5 V 5% Core/ 1.8 V 0.2 V Output Operating Supply Mixed 2.5 V 5% Core /1.5 V 0.15 V Output Operating Supply Two Separate Output Bank Power Supplies Industrial Temperature Range: 40C to 85C These are PbFree Devices Applications End Products Clock Distribution Servers Networking and Communications Ethernet Switch/Routers High End Computing ATE Wireless and Wired Infrastructure Test and Measurement Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: April, 2021 Rev. 2 NB3F8L3005C/DNB3F8L3005C BANK A VDDOA VDD GND Q0 SEL Q1 CLK CLK XTAL IN BANK B OSC XTAL OUT VDDOB Q2 Q3 Q4 OE SYNC Figure 1. Simplified Logic Diagram Exposed Pad (EP) 24 23 22 21 20 19 VDDOB 1 18 GND Q4 VDDOA 2 17 GND Q0 3 16 NB3F8L3005C 4 15 GND Q3 Q1 5 14 VDD0B VDDOA 6 13 Q2 78 9 10 11 12 Figure 2. Pinout Configuration (Top View) www.onsemi.com 2 OE GND VDD VDD SEL XTAL IN XTAL OUT CLK GND CLK GND GND