2.5 V / 3.3 V / 5.0 V 1:4 Clock Fanout Buffer NB3L553 Description The NB3L553 is a low skew 1to 4 clock fanout buffer, designed for clock distribution in mind. The NB3L553 specifically guarantees low www.onsemi.com output to output skew. Optimal design, layout and processing minimize skew within a device and from device to device. MARKING DIAGRAMS* 8 Features SOIC8 3L553 Input/Output Clock Frequency up to 200 MHz 8 D SUFFIX ALYW Low Skew Outputs (35 ps), Typical CASE 751 1 RMS Phase Jitter (12 kHz 20 MHz): 29 fs (Typical) 1 Output goes to ThreeState Mode via OE 3L553 = Specific Device Code Operating Range: V = 2.375 V to 5.25 V A = Assembly Location DD L = Wafer Lot 5 V Tolerant Input Clock I CLK Y = Year Ideal for Networking Clocks W = Work Week = PbFree Package Packaged in 8pin SOIC Industrial Temperature Range These are PbFree Devices 1 DFN8 6P M MN SUFFIX 1 CASE 506AA Q1 6P = Specific Device Code M = Date Code Q2 = PbFree Package I CLK (Note: Microdot may be in either location) Q3 *For additional marking information, refer to Application Note AND8002/D. Q4 PINOUT DIAGRAM OE 1 8 V OE DD Figure 1. Block Diagram 2 7 Q3 Q0 3 6 Q2 Q1 4 5 GND I CLK ORDERING INFORMATION Device Package Shipping NB3L553DG SOIC8 98 Units/Rail (PbFree) NB3L553DR2G SOIC8 2500/Tape & Reel (PbFree) NB3L553MNR4G DFN8 1000/Tape & Reel (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: March, 2021 Rev. 11 NB3L553/DNB3L553 Table 1. OE, OUTPUT ENABLE FUNCTION OE Function 0 Disable 1 Enable Table 2. PIN DESCRIPTION Pin Name Type Description 1 V Power Positive supply voltage (2.375 V to 5.25 V) DD 2 Q0 (LV)CMOS/(LV)TTL Output Clock Output 0 3 Q1 (LV)CMOS/(LV)TTL Output Clock Output 1 4 GND Power Negative supply voltage Connect to ground, 0 V 5 I (LV)CMOS Input Clock Input. 5.0 V tolerant CLK 6 Q2 (LV)CMOS/(LV)TTL Output Clock Output 2 7 Q3 (LV)CMOS/(LV)TTL Output Clock Output 3 8 OE (LV)TTL Input V for normal operation. Pin has no internal pullup or pull down resistor for open DD condition default. Use from 1 to 10 kOhms external resistor to force an open con- dition default state. EP Thermal Exposed Pad (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave uncon- nected, floating open. www.onsemi.com 2