2.5 V/3.3 V 1:5 LVPECL Fanout Buffer NB3L853141 Description The NB3L853141 is a low skew 1:5 LVPECL Clock fanout buffer designed explicitly for low output skew applications. wwwwww..onsemi.comonsemi.com The NB3L853141 features a multiplexed input which can be driven by either a differential or singleended input to allow for the MARKING distribution of a lower speed clock along with the high speed system DIAGRAM clock. The SEL pin will select the differential clock inputs, CLK0 & NB3L CLK0, when LOW (or left open and pulled LOW by the internal 3141 pulldown resistor). When SEL is HIGH, the singleended CLK1 TSSOP20 ALYW input is selected. DT SUFFIX The common enable (EN) is synchronous so that the outputs will CASE 948E only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is A = Assembly Location WL = Wafer Lot enabled/disabled as can happen with an asynchronous control. The YY = Year internal flip flop is clocked on the falling edge of the input clock, WW = Work Week therefore, all associated specification limits are referenced to the G = PbFree Package negative edge of the clock input. Features D EN 700 MHz Maximum Clock Output Frequency Q Q0 CLK0 and CLK0 can Accept Differential LVPECL, LVDS, HCSL, Q0 LVHSTL, SSTL, LVCMOS CLK0 0 Q1 CLK1 can Accept LVCMOS and LVTTL CLK0 Q1 Five Differential LVPECL Clock Outputs + Q2 1.5 ns Maximum Propagation Delay 1 Q2 CLK1 Operating Range: V = 2.375 V to 3.8 V CC Q3 SEL Q3 LVCMOS Compatible Control Inputs Q4 Selectable Differential or LVCMOS Clock Inputs Q4 Synchronous Clock Enable Figure 1. Simplified Logic Diagram of 30 ps Max. Skew Between Outputs NB3L853141 40C to +85C Ambient Operating Temperature Range TSSOP20 Package These Devices are PbFree, Halogen Free/BFR Free and are RoHS ORDERING INFORMATION Compliant Device Package Shipping Applications 2500 / Tape TSSOP20 NB3L853141DTR2G Computing and Telecom & Reel (PbFree) Routers, Servers and Switches For information on tape and reel specifications, Backplanes including part orientation and tape sizes, please re- fer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: May, 2021 Rev. 3 NB3L853141/DNB3L853141 V EN V NC CLK1 CLK0 CLK0 NC SEL V CC CC EE Table 1. FUNCTION TABLE 20 19 18 17 16 15 14 13 12 11 CLK0 CLK1 SEL EN Q L X L L L H X L L H X L H L L X H H L H X X X H L* *On next negative transition of CLK0 or CLK1 X = Dont Care 1 2354 678 9 10 Q0 Q1 Q2 Q3 Q4 Q0 Q1 Q2 Q3 Q4 Note: All V and V pins must be externally connected to CC EE Power Supply to guarantee proper operation. Figure 1. Pinout (Top View) and Logic Diagram Table 2. PIN DESCRIPTION Open Pin Number Name I/O Default Description 1 Q0 LVPECL Output NonInverted Differential Clock Output 2 Q0 LVPECL Output Inverted Differential Clock Output 3 Q1 LVPECL Output NonInverted Differential Clock Output 4 Q1 LVPECL Output Inverted Differential Clock Output 5 Q2 LVPECL Output NonInverted Differential Clock Output 6 Q2 LVPECL Output Inverted Differential Clock Output 7 Q3 LVPECL Output NonInverted Differential Clock Output 8 Q3 LVPECL Output Inverted Differential Clock Output 9 Q4 LVPECL Output NonInverted Differential Clock Output 10 Q4 LVPECL Output Inverted Differential Clock Output 11 VEE Power Negative Supply Voltage 12 SEL LVCMOS / LVTTL Low Clock Select Input. When HIGH, selects CLK1 input. When LOW, Input selects CLK0, CLK0 inputs. Internal Pulldown Resistor. 13 NC No Connect 14 CLK0 MultiLevel Input High Inverted Differential Clock Input. Internal Pullup Resistor. 15 CLK0 MultiLevel Input Low NonInverted Differential Clock Input. Internal Pulldown Resistor. 16 CLK1 LVCMOS/LVTTL Low Singleended Clock Input. Internal Pulldown Resistor. Input 17 NC No Connect 18 VCC Power Positive Supply Voltage 19 EN LVCMOS/LVTTL Low Synchronous Clock Enable Input. When Low, outputs are enabled. Input When High, outputs are disabled Low. Internal Pulldown Resistor. 20 VCC Power Positive Supply Voltage All VCC and VEE pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with 0.01 F to GND. www.onsemi.com 2