NB3L8543S 2.5 V/3.3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs with Clock Enable and Clock www.onsemi.com Select Description MARKING The NB3L8543S is a high performance, low skew 1to4 LVDS DIAGRAM Clock Fanout Buffer. The NB3L8543S features a multiplexed input which can be driven NB3L by either a differential or singleended input to allow for the 8543 distribution of a lower speed clock along with the high speed system TSSOP20 ALYW clock. DT SUFFIX The CLK SEL pin will select the differential CLK and CLK inputs CASE 948E when LOW (or left open and pulled LOW by the internal pulldown resistor). When CLK SEL is HIGH, the differential PCLK and PCLK A = Assembly Location inputs are selected. L = Wafer Lot Y = Year The common clock enable pin, CLK EN, is synchronous so that the W = Work Week outputs will only be enabled/disabled when they are already in the = PbFree Package LOW state. This avoids any chance of generating a runt clock pulse on (Note: Microdot may be in either location) the outputs during asynchronous assertion/deassertion of the clock enable pin. The internal flip flop is clocked on the falling edge of the input clock therefore, all associated specification limits are + referenced to the negative edge of the clock input. D CLK EN Features Q Q0 Four Differential LVDS Output Pairs Q0 CLK Two Selectable Differential Clock Inputs 0 Q1 CLK CLK/CLK Can Accept LVPECL, LVDS, HCSL, SSTL and HSTL Q1 + PCLK/PCLK Can Accept LVPECL, LVDS, CML and SSTL Q2 PCLK Maximum Output Frequency: 650 MHz Q2 1 PCLK Q3 Additive Phase Jitter, RMS: 50 fs (typical) + Q3 Output Skew: 40 ps (maximum) CLK SEL + Parttopart Skew: 200 ps (maximum) OE Propagation Delay: 1.9 ns (maximum) Operating Range: V = 2.5 V 5% or 3.3 V 10% DD Figure 1. Simplified Logic Diagram 40C to +85C Ambient Operating Temperature Range TSSOP20 Package ORDERING INFORMATION These are PbFree Devices See detailed ordering and shipping information on page 10 of this data sheet. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: October, 2014 Rev. 1 NB3L8543E/DNB3L8543S GND 1 20 Q0 CLK EN 2 19 Q0 CLK SEL 3 18 V DD 17 Q1 4 CLK 16 Q1 CLK 5 PCLK 15 6 Q2 PCLK 14 7 Q2 OE 13 8 GND GND 12 Q3 9 V 11 Q3 DD 10 Figure 2. Pinout Diagram (Top View) Table 1. PIN DESCRIPTION Open Default Number Name I/O Description 1, 9, 13 GND Power Negative (Ground) Power Supply pins must be externally connected to power supply to guarantee proper operation. 2 CLK EN NC Pullup Synchronized Clock Enable when HIGH. When LOW, outputs are disabled (Qx HIGH, Qx LOW). See Figure 3. 3 CLK SEL NC Pulldown Clock Input Select (HIGH selects PCLK/PCLK, LOW selects CLK/ CLK input 4 CLK Input Pulldown True Standard Clock Input. Float open when unused. 5 CLK Input Pullup Invert Standard Clock Inputs. Float open when unused. 6 PCLK Input Pulldown True Peripheral Clock Input. Float open when unused. 7 PCLK Input Pullup Invert Peripheral Clock Inputs. Float open when unused. 8 OE NC Pullup Output Enable Control. When HIGH, the outputs are active and en- abled. When LOW, the outputs are high impedance disabled. 10 ,18 VDD Power Positive Power Supply pin must be externally connected to power supply to guarantee proper operation. 11, 14, 16, Q 3:0 Output Invert LVDS Outputs 19 12, 15, 17, Q 3:0 Output True LVDS Outputs 20 www.onsemi.com 2