NB3M8302C 3.3 V 200 MHz 1:2 LVCMOS/LVTTL Low Skew Fanout Buffer Description www.onsemi.com The NB3M8302C is 1:2 fanout buffer with LVCMOS/LVTTL input and output. The device supports the core supply voltage of 3.3 V (V DD MARKING pin) and output supply voltage of 2.5 V or 3.3 V (V pin). The DDO DIAGRAMS* V pin powers the two single ended LVCMOS/LVTTL outputs. DDO 8 8 The NB3M8302C is Form, Fit and Function (pin to pin) compatible 8302C to ICS8302 and ICS8302I. The NB3M8302C is qualified for industrial 1 ALYW operating temperature range. SOIC8 D SUFFIX 1 Features CASE 751 Input Clock Frequency up to 200 MHz A = Assembly Location Low Output to Output Skew: 25 ps typical L = Wafer Lot Low Part to Part Skew: 250 ps typical Y = Year W = Work Week Low Additive RMS Phase Jitter = PbFree Package Input Clock Accepts LVCMOS/ LVTTL Levels (Note: Microdot may be in either location) Operating Voltage: Core Supply: V = 3.3 V 5% DD Output Supply: V = 3.3 V 5% or 2.5 V 5% DDO ORDERING INFORMATION See detailed ordering and shipping information in the package Operating Temperature Range: dimensions section on page 5 of this data sheet. Industrial: 40C to +85C These Devices are PbFree and are RoHS Compliant Figure 1. Block Diagram Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: December, 2014 Rev. 3 NB3M8302C/DNB3M8302C Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Number Name Type Description 1, 6 VDDO Output Power Clock output Supply pin. 2 VDD Input and Core Power Input and Core Supply pin. 3 CLK LVCMOS/LVTTL Input Clock Input. Internally pulldown. 4, 7 GND Ground Supply Ground. 5 Q1 LVCMOS/LVTTL Output LVCMOS/LVTTL Clock output. 8 Q0 LVCMOS/LVTTL Output LVCMOS/LVTTL Clock output. Table 2. MAXIMUM RATINGS Symbol Parameter Condition Min Max Unit V V Power Supply 4.6 V DD, DDO V Input Voltage 0.5 VDD + 0.5 V V I T Storage Temperature 65 +150 C stg Thermal Resistance (Junction to Ambient) C/W JA SOIC8 0 lfpm 80 500 lfpm 55 Thermal Resistance (Junction to Case) 1217 C/W JC (Note 1) T Wave Solder 3 sec 265 C sol MSL Moisture Sensitivity Indefinite Time Out of Drypack SOIC8 (Note 2) Level 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board 2S2P (2 signal, 2 power) 2. For additional information, see Application Note AND8003/D. www.onsemi.com 2