3.3 V Differential 1:10 Fanout Clock Driver with HCSL Outputs NB3N111K Description www.onsemi.com The NB3N111K is a differential 1:10 Clock fanout buffer with Highspeed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N111K is designed with PCI Express HCSL clock distribution and FBDIMM applications in mind. 1 32 Inputs can directly accept differential LVPECL, LVDS, and HCSL QFN32 signals per Figures 7, 8, and 9. Single ended LVPECL, HCSL, MN SUFFIX CASE 488AM LVCMOS, or LVTTL levels are accepted with a proper external V th reference supply per Figures 4 and 10. Input pins incorporate separate internal 50 termination resistors allowing additional single ended MARKING DIAGRAM* system interconnect flexibility. 1 Output drive current is set by connecting a 475 resistor from IREF (Pin 1) to GND per Figure 6. Outputs can also interface to LVDS NB3N 111K receivers when terminated per Figure 11. AWLYYWWG The NB3N111K specifically guarantees low outputtooutput skew. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take A = Assembly Location advantage of the NB3N111Ks performance to distribute low skew WL = Wafer Lot clocks across the backplane or the motherboard. YY = Year WW = Work Week Features G = PbFree Package Typical Input Clock Frequency 100, 133, 166, or 400 MHz *For additional marking information, refer to Application Note AND8002/D. 220 ps Typical Rise and Fall Times 800 ps Typical Propagation Delay Q0 tpd 100 ps Maximum Propagation Delay Variation per Diff Pair 0.1 ps Typical RMS Additive Phase Jitter VTCLK Q0 LVDS Output Levels Optional with Interface Termination Q1 Operating Range: V = 3.0 V to 3.6 V with GND = 0 V CC Typical HCSL Output Levels (700 mV PeaktoPeak) Q1 CLK CLK LVDS Output Levels with Interface Termination These are PbFree Devices Q8 Applications VTCLK Q8 Clock Distribution Q9 PCIe I, II, III V Networking CC IREF Q9 GND High End Computing R REF Routers End Products Figure 1. Simplified Logic Diagram Servers FBDIMM Memory Card ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: May, 2021 Rev. 6 NB3N111K/DNB3N111K Exposed Pad (EP) 32 31 30 29 28 27 26 25 1 24 IREF VCC 2 23 VTCLK Q3 3 22 CLK Q3 4 21 Q4 CLK NB3N111K 5 20 VTCLK Q4 Q5 6 19 Q9 Q9 7 18 Q5 8 17 VCC GND 9 10 11 12 1314 1516 Figure 2. Pinout Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 IREF Use the IREF pin to set the output drive. Connect a 475 RREF resistor from the IREF pin to GND to produce 2.6 mA of IREF current. A current mirror multiplies IREF by a factor of 5.4x to force 14 mA through a 50 output load. See Figures 6 and 12. 2, 5 VTCLK, Internal 50 Termination Resistor connection Pins. In the differential VTCLK configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied then the device may be susceptible to selfoscillation. 3 CLK LVPECL, HCSL, Clock and Data (TRUE) Input LVDS Input 4 CLK LVPECL, HCSL, Clock and Data (INVERT) Input LVDS Input 6, 10, 12, 14, 18, 20, Q 90 HCSL or LVDS Output (INVERT) (Note 1) 22, 26, 28, 30 (Note 1) Output 7, 11, 13, 15, 19, 21, Q 90 HCSL or LVDS Output (TRUE) (Note 1) 23, 27, 29, 31 (Note 1) Output 8 GND Supply Ground. GND pin must be externally connected to power supply to guarantee proper operation. 9, 16, 17, 24, 25, 32 VCC Positive Voltage Supply pin. VCC pins must be externally connected to a power supply to guarantee proper operation. Exposed Pad EP GND Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heatsinking conduit for proper thermal operation and electrically connected to the circuit board ground (GND). 1. Outputs can also interface to LVDS receiver when terminated per Figure 11. www.onsemi.com 2 VCC VCC Q0 Q8 Q0 Q8 Q1 Q7 Q1 Q7 Q2 Q6 Q6 Q2 VCC VCC