NB3V110xC Series 3.3V/2.5V/1.8V LVCMOS Low Skew Fanout Buffer Family Description www.onsemi.com The NB3V110xC are a modular, highperformance, lowskew, general purpose LVCMOS clock buffer family. The family of devices is designed with a modular approach. Four different fanout variations, 1:2, 1:3, 1:4, 1:6 and 1:8, are available. All of the devices are pin compatible to each other for easy handling. All family members share the same high performing characteristics like low TSSOP8 TSSOP14 TSSOP16 DT SUFFIX DT SUFFIX DT SUFFIX additive jitter, low skew, and wide operating temperature range. The CASE 948S CASE 948G CASE 948F NB3V110xC supports an asynchronous output enable control (OE) which switches the outputs into a low state when OE is low. The NB3V110xC devices operate in a 3.3 V, 2.5 V and 1.8 V environment and are characterized for operation from 40C to 105C. WDFN8, 2x2 Features MT SUFFIX CASE 511AT Operating Temperature Range: 40C to 105C HighPerformance 1:2, 1:3, 1:4, 1:6, 1:8 LVCMOS Clock Buffer MARKING DIAGRAMS Available in 8, 14, 16Pin TSSOP and WDFN8 Packages 8 Very Low OutputtoOutput Skew < 50 ps 16 14 Very Low Additive Jitter < 200 fs 1108 10x 1106 V V Supply Voltage: 3.3 V, 2.5 V or 1.8 V YWW ALYW ALYW A f = 250 MHz for 3.3 V f = 180 MHz for 2.5 V max max f = 133 MHz for 1.8 V 1 max 1 1 These Devices are PbFree and are RoHS Compliant TSSOP8 TSSOP14 TSSOP16 BLOCK DIAGRAM 1 0X M LV LV Q0 CLKIN CMOS CMOS LV WDFN8 Q1 CMOS A = Assembly Location LV Q2 CMOS M = Date Code L = Wafer Lot Y = Year LV Q3 CMOS W, WW = Work Week = PbFree Package (Note: Microdot may be in either location) LV ORDERING INFORMATION Qn CMOS See detailed ordering, marking and shipping information on page 9 of this data sheet. OE Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: January, 2017 Rev. 3 NB3V1102C/DNB3V110xC Series CLKIN 1 16 Q1 CLKIN OE 2 1 14 Q1 15 Q3 OE Q0 3 14 2 13 Q3 VDD CLKIN 1 8 Q1 Q0 GND 13 4 Q2 3 12 VDD NB3V1108C OE NB3V1102C 2 7 NC/Q3 GND VDD 5 12 NB3V1103C 4 11 Q2 GND NB3V1106C Q0 VDD 3 6 NB3V1104C VDD Q4 6 11 5 10 GND Q5 NC/Q2 GND 4 5 Q4 GND 10 7 VDD 6 9 Q5 TSSOP8 and WDFN8 Q6 9 GND 8 Q7 7 8 VDD TSSOP14 TSSOP16 Figure 1. Pin Configuration Table 1. PIN DESCRIPTION LVCMOS Clock LVCMOS Clock Device Device Input Output Enable LVCMOS Clock Output Supply Voltage Ground Devices CLKIN OE Q0, Q1, ... Q7 VDD GND NB3V1102C 1 2 3, 8 6 4 NB3V1103C 1 2 3, 8, 5 6 4 NB3V1104C 1 2 3, 8, 5, 7 6 4 NB3V1106C 1 2 3, 14, 11, 13, 6, 9 5, 8, 12 4, 7, 10 NB3V1108C 1 2 3, 16, 13, 15, 6, 11, 8, 9 5, 10, 14 4, 7, 12 NOTE: Pins not mentioned in the table are NC. Table 2. OUTPUT LOGIC TABLE INPUTS OUTPUTS CLKIN OE Qn X L L L H L H H H Table 3. ATTRIBUTES Characteristic Value Unit ESD Protection Human Body Model (HBM) per ANSI/ESDA/JEDEC JS0012014 5000 V Charged Device Model (CDM) per ANSI/ESDA/JEDEC JS0022014 1500 V Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1) Level 1 Meets or exceeds JEDEC Spec JESD78D (LU) IC Latchup Test 2 1. JEDEC standard multilayer board 2S2P (2 signal, 2 power) with a large copper heat spreader (20 mm , 2 oz.) www.onsemi.com 2