NB3V8312C Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer The NB3V8312C is a high performance, low skew LVCMOS fanout buffer which can distribute 12 ultralow jitter clocks from an NB3V8312C Exposed Pad (EP) 32 31 30 29 28 27 26 25 24 GND 1 Q4 23 V DD 2 V DDO GND 1 24 Q4 22 3 CLK EN Q5 V 2 23 DD V DDO 21 4 CLK GND 3 22 Q5 CLK EN NB3V8312C 21 20 CLK 4 5 GND GND Q6 NB3V8312C GND 5 20 Q6 19 6 OE V DDO OE 6 19 V DDO 7 18 V Q7 DD V 7 18 DD Q7 8 17 GND GND GND 17 GND 8 910 11 12 13 14 15 16 Figure 2. LQFP32 Pinout Configuration Figure 3. QFN32 Pinout Configuration (Top View) (Top View) Table 1. PIN DESCRIPTION Open Pin Name I/O Default Description 1, 5, 8, 12, 16, 17, GND Power Ground, Negative Power Supply 21, 25, 29 2, 7 VDD Power Positive Supply for Core and Inputs 3 CLK EN Input High Synchronous Clock Enable Input. When High, outputs are enabled. When Low, outputs are disabled Low. Internal Pullup Resistor. 4 CLK Input Low Singleended Clock input LVCMOS/LVTTL. Internal Pulldown Resistor. 6 OE Input High Output Enable. Internal Pullup Resistor. 9, 11, 13, 15, 18, Q11, Q10, Q9, Q8, Output Singleended LVCMOS/LVTTL outputs 20, 22, 24, 26, 28, Q7, Q6, Q5, Q4, 30, 32 Q3, Q2, Q1, Q0 10, 14, 19, 23, 27, VDDO Power Positive Supply for Outputs 31 EP The Exposed Pad (EP) on the package bottom is ther- mally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heatsinking conduit. The pad is connected to the die and must only be connected electrically to GND on the PC board. 1. All VDD, VDDO and GND pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with 0.01 F to GND.