NB4N111K 3.3V Differential In 1:10 Differential Fanout Clock Driver with HCSL Level Output NB4N111K Exposed Pad (EP) VCC I 1 24 REF VTCLK 23 Q3 2 CLK Q3 3 22 CLK 4 21 Q4 NB4N111K VTCLK 20 Q4 5 Q9 6 19 Q5 Q9 7 18 Q5 GND VCC 8 17 Figure 2. Pinout Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 I Output Output current programming pin. Connect to GND. (See Figure 9). REF 2, 5 VTCLK, Internal 50 Termination Resistor connection Pins. In the differential configuration VTCLK when the input termination pins are connected to the common termination voltage, and if no signal is applied then the device may be susceptible to selfoscillation. 3 CLK LVPECL Input CLOCK Input (TRUE) 4 CLK LVPECL Input CLOCK Input (INVERT) 8 GND Supply Ground. GND pin must be externally connected to power supply to guarantee proper operation. 9, 16, 17, 24, 25, 32 V Positive Supply pins. V pins must be externally connected to a power supply to CC CC guarantee proper operation. 6, 10, 12, 14, 18, 20, Q 090 HCSL or Noninverted Clock Output. (For LVDS levels see Figure 15) 22, 26, 28, 30 LVDS Output 7, 11, 13, 15, 19, 21, Q 090 HCSL or Inverted Clock Output. (For LVDS levels see Figure 15) 23, 27, 29, 31 LVDS Output Exposed Pad EP GND Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heat sinking conduit for proper thermal operation. (Note 1) 1. The exposed pad must be connected to the circuit board ground.