3.3 V, 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/Buffer/Translator NB4N11M Description www.onsemi.com The NB4N11M is a differential 1 to 2 clock/data distribution/translation chip with CML output structure, targeted for 8 high speed clock/data applications. The device is functionally 1 equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device produces two identical differential output copies of clock or TSSOP8 data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such, DT SUFFIX NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and CASE 948R other clock/data distribution applications. Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS MARKING DIAGRAM* (See Table 5). The CML outputs are 16 mA open collector (See Figure 18) which requires resistor (R ) load path to V L TT 8 termination voltage. The open collector CML outputs must be E11M terminated to V at power up. Differential outputs produces TT ALYW currentmode logic (CML) compatible levels when receiver loaded with 50 or 25 loads connected to 1.8 V, 2.5 V or 3.3 V supplies 1 (see Figure 19). This simplifies device interface by eliminating a need for coupling capacitors. A = Assembly Location The device is offered in a small 8pin TSSOP package. L = Wafer Lot Application notes, models, and support documentation are available Y = Year at www.onsemi.com. W = Work Week = PbFree Package Features (Note: Microdot may be in either location) Maximum Input Clock Frequency > 2.5 GHz *For additional marking information, refer to Maximum Input Data Rate > 2.5 Gb/s Application Note AND8002/D. Typically 1 ps of RMS Clock Jitter Typically 10 ps of Data Dependent Jitter 2.5 Gb/s, R = 25 L Q0 420 ps Typical Propagation Delay Q0 150 ps Typical Rise and Fall Times D Operating Range: V = 3.0 V to 3.6 V with V = 0 V and CC EE V = 1.8 V to 3.6 V TT D Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices Q1 These Devices are PbFree, Halogen Free and are RoHS Compliant Q1 Figure 1. Functional Block Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Semiconductor Components Industries, LLC, 2005 1 Publication Order Number: May, 2021 Rev. 3 NB4N11M/DNB4N11M Q0 1 8 V CC Q0 2 7 D 6 D Q1 3 Q1 4 5 V EE Figure 2. Pinout (Top View) and Logic Diagram Table 1. Pin Description Pin Name I/O Description 1 Q0 CML Output Noninverted differential output. Typically receiver terminated with 50 resistor to V . Open collector CML outputs must be terminated to V at TT TT powerup. 2 Q0 CML Output Inverted differential output. Typically receiver terminated with 50 resistor to V . Open collector CML outputs must be terminated to V at powerup. TT TT 3 Q1 CML Output Noninverted differential output. Typically receiver terminated with 50 resistor to V . Open collector CML outputs must be terminated to V at TT TT powerup. 4 Q1 CML Output Inverted differential output. Typically receiver terminated with 50 resistor to V . Open collector CML outputs must be terminated to V at powerup. TT TT 5 V Negative supply voltage. EE 6 D LVPECL, CML, HSTL, Inverted differential input. LVCMOS, LVDS, LVTTL Input 7 D LVPECL, CML, HSTL, Noninverted differential input. LVCMOS, LVDS, LVTTL Input 8 V Positive supply voltage. CC www.onsemi.com 2