NB4N316M 3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis 2.0 GHz Clock / 2.5 Gb/s Data www.onsemi.com The NB4N316M is a differential Clock or Data receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, MARKING DIAGRAM* or LVDS. These signals will be translated to CML, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N316M is ideal 8 8 for SONET, GigE, Fiber Channel, Backplane and other Clock or Data 1 E316 distribution applications. The CML outputs are 16 mA open collector ALYW TSSOP8 (see Figure 18) which requires resistor (R ) load path to V L TT DT SUFFIX termination voltage (see Figure 19). The open collector CML outputs 1 CASE 948R must be terminated to V at power up. The differential outputs TT produce CurrentMode Logic (CML) compatible levels when the A = Assembly Location receiver is loaded with 50 or 25 loads connected to 1.8 V, 2.5 V L = Wafer Lot or 3.3 V supplies. This simplifies device interface by eliminating a Y = Year need for coupling capacitors. W = Work Week The NB4N316M features an input threshold hysteresis of = PbFree Package approximately 25 mV, providing increased noise immunity and stability. (Note: Microdot may be in either location) The device is offered in a small 8pin TSSOP package (MSOP8 *For additional marking information, refer to compatible). Application notes, models, and support documentation Application Note AND8002/D. are available at www.onsemi.com. Features Maximum Input Clock Frequency > 2.0 GHz D Q Maximum Input Data Rate > 2.5 Gb/s Q D Typically 1 ps of RMS Clock Jitter Typically 10 ps of Data Dependent Jitter Figure 1. Functional Block Diagram 550 ps Typical Propagation Delay 150 ps Typical Rise and Fall Times Differential CML Outputs ORDERING INFORMATION 25 mV of Receiver Input Threshold Hysteresis See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. Operating Range: V = 3.0 V to 3.6 V with V = 0 V and CC EE V = 1.8 V to 3.6 V TT Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices 40C to +85C Ambient Operating Temperature These are PbFree Devices* *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 6 NB4N316M/DNB4N316M NC 1 8 V CC D 2 7 Q D 3 6 Q V45 V BB EE Figure 2. Pinout (Top View) and Logic Diagram Table 1. Pin Description Pin Name I/O Description 1 NC No Connect. 2 D ECL, CML, LVCMOS, LVDS, Noninverted Differential Input. (Note 1) LVTTL Input 3 D ECL, CML, LVCMOS, LVDS, Inverted Differential Input. (Note 1) LVTTL Input 4 V Internally Generated Reference Voltage Supply. BB 5 V Negative Supply Voltage. EE 6 Q CML Output Inverted Differential Output. Typically Terminated with 50 Resistor to V . TT 7 Q CML Output Noninverted Differential Output. Typically Terminated with 50 Resistor to V . TT 8 V Positive Supply Voltage. CC 1. In the differential configuration if no signal is applied on D/D input, then the device will be susceptible to selfoscillation. www.onsemi.com 2