NB6L11 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator NB6L11 Q0 1 8 V CC R Q0 2 2 7 D R 1 R 1 6 D Q1 3 R 2 Q1 4 5 V EE Figure 1. Pinout (Top View) and Logic Diagram Table 1. PIN DESCRIPTION Pin Name I/O Default State Description 1 Q0 ECL Output Noninverted differential clock/data output 0. Typically termin- ated with 50 Resistor to V = V 2 V. TT CC 2 Q0 ECL Output Inverted differential clock/data output 0. Typically terminated with 50 resistor to V = V 2 V. TT CC 3 Q1 ECL Output Noninverted differential clock/data output 1. Typically termin- ated with 50 resistor to V = V 2 V. TT CC 4 Q1 ECL Output Inverted differential clock/data output 1. Typically terminated with 50 resistor to V = V 2 V. TT CC 5 V Negative power supply voltage EE 6 D LVDS, CML, LVPECL, LVNECL, HIGH Inverted differential clock/data input. Internal 37.5 k to V and CC LVCMOS, LVTTL Input 75 k to V . EE 7 D LVDS, CML, LVPECL, LVNECL, LOW Noninverted differential clock/data input. Internal 75 k to V CC LVCMOS, LVTTL Input and 37.5 k to V . EE 8 V Positive power supply voltage CC Table 2. ATTRIBUTES Characteristics Value Internal Input Resistor R1 37.5 k Internal Input Resistor R2 75 k ESD Protection Human Body Model > 2 kV Machine Model > 100 V Charged Device Model > 1 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg PbFree Pkg SOIC8 Level 1 Level 1 TSSOP8 Level 1 Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 167 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.