NB6L11M 2.5V / 3.3V 1:2 Differential CML Fanout Buffer MultiLevel Inputs w/ Internal Termination NB6L11M V V V V Exposed Pad (EP) CC EE EE CC 16 15 14 13 VTD Q0 1 12 D 2 11 Q0 NB6L11M D Q1 3 10 VTD Q1 4 9 56 7 8 V V V V CC REFAC EE CC Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VTD Internal 50 Termination Pin for D input. 2 D ECL, CML, Noninverted Differential Input. Note 1. Internal 50 Resistor to Termination Pin, VTD. LVCMOS, LVDS, LVTTL Input 3 D ECL, CML, Inverted Differential Input. Note 1. Internal 50 Resistor to Termination Pin, VTD. LVCMOS, LVDS, LVTTL Input 4 VTD Internal 50 Termination Pin for D input. 5 V Positive Supply Voltage CC 6 V Output Reference Voltage for direct or capacitor coupled inputs REFAC 7 V Negative Supply Voltage EE 8 V Positive Supply Voltage CC 9 Q1 CML Output Inverted Differential Output. Typically Terminated with 50 Resistor to V . CC 10 Q1 CML Output Noninverted Differential Output. Typically Terminated with 50 Resistor to V . CC 11 Q0 CML Output Inverted Differential Output. Typically Terminated with 50 Resistor to V . CC 12 Q0 CML Output Noninverted Differential Output. Typically Terminated with 50 Resistor to V . CC 13 V Positive Supply Voltage CC 14 V Negative Supply Voltage EE 15 V Negative Supply Voltage EE 16 V Positive Supply Voltage CC EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board. 1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage or left open, and if no signal is applied on D/D input, then, the device will be susceptible to selfoscillation. 2. All V and V pins must be externally connected to a power supply for proper operation. CC EE