NB6N11S 3.3 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will www.onsemi.com accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical MARKING copies of Clock or Data will be distributed, operating up to 2.0 GHz or DIAGRAM* 2.5 Gb/s, respectively. As such, the NB6N11S is ideal for SONET, 16 GigE, Fiber Channel, Backplane and other Clock or Data distribution 1 applications. 1 NB6N The NB6N11S has a wide input common mode range from 11S GND + 50 mV to V 50 mV. Combined with the 50 internal QFN16 CC ALYW MN SUFFIX termination resistors at the inputs, the NB6N11S is ideal for CASE 485G translating a variety of differential or singleended Clock or Data signals to 350 mV typical LVDS output levels. The NB6N11S is functionally equivalent to the EP11, LVEP11, A = Assembly Location SG11 or 7L11M devices and is offered in a small, 3 mm X 3 mm, L = Wafer Lot 16QFN package. Application notes, models, and support Y = Year documentation are available at www.onsemi.com. W = Work Week The NB6N11S is a member of the ECLinPS MAX family of high = PbFree Package performance products. (Note: Microdot may be in either location) Features *For additional marking information, refer to Application Note AND8002/D. Maximum Input Clock Frequency > 2.0 GHz Maximum Input Data Rate > 2.5 Gb/s 1 ps Maximum of RMS Clock Jitter Typically 10 ps of Data Dependent Jitter Q0 380 ps Typical Propagation Delay V Q0 TD 120 ps Typical Rise and Fall Times Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and D SG Devices D These are PbFree Devices V TD Q1 Q1 Figure 1. Logic Diagram ORDERING INFORMATION Device DDJ = 10 ps See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. TIME (58 ps/div) Figure 2. Typical Output Waveform at 2.488 Gb/s with 231 PRBS 2 (V = 400 mV Input Signal DDJ = 14 ps) INPP Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: November, 2014 Rev. 7 NB6N11S/D VOLTAGE (130 mV/div)NB6N11S Exposed Pad (EP) V V V V CC CC CC CC 16 15 14 13 Q0 1 12 V TD Q0 2 11 D NB6N11S Q1 3 10 D Q1 4 9 V TD 56 7 8 V NC V V CC EE EE Figure 3. NB6N11S Pinout, 16pin QFN (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 Q0 LVDS Output Noninverted D output. Typically loaded with 100 receiver termination resistor across differential pair. 2 Q0 LVDS Output Inverted D output. Typically loaded with 10 receiver termination resistor across differential pair. 3 Q1 LVDS Output Noninverted D output. Typically loaded with 100 receiver termination resistor across differential pair. 4 Q1 LVDS Output Inverted D output. Typically loaded with 100 receiver termination resistor across differential pair. 5 V Positive Supply Voltage CC 6 NC No Connect 7 V Negative Supply Voltage EE 8 V Negative Supply Voltage EE 9 V Internal 50 termination pin for D TD 10 D LVPECL, CML, LVDS, Inverted Differential Clock/Data Input (Note 1) LVCMOS, LVTTL 11 D LVPECL, CML, LVDS, Noninverted Differential Clock/Data Input (Note 1) LVCMOS, LVTTL 12 V Internal 50 termination pin for D TD 13 V Positive Supply Voltage CC 14 V Positive Supply Voltage CC 15 V Positive Supply Voltage CC 16 V Positive Supply Voltage CC EP Exposed pad. The exposed pad (EP) on the package bottom must be attached to a heatsinking conduit. The exposed pad may only be electrically connected to V . EE 1. In the differential configuration when the input termination pins (VTD/VTD) are connected to a common termination voltage or left open, and if no signal is applied on D/D inputs, then the device will be susceptible to self oscillation. www.onsemi.com 2