2.5 V/3.3 V 1:8 CML Fanout MultiLevel Inputs w/ Internal Termination NB7L1008M Description www.onsemi.com The NB7L1008M is a high performance differential 1:8 Clock/Data fanout buffer. The NB7L1008M produces eight identical output copies MARKING of Clock or Data operating up to 6 GHz or 10.7 Gb/s, respectively. As DIAGRAM* such, the NB7L1008M is ideal for SONET, GigE, Fiber Channel, 32 Backplane and other Clock/Data distribution applications. The 1 differential inputs incorporate internal 50 termination resistors that 1 32 NB7L are accessed through the VT pin. This feature allows the NB7L1008M QFN32 1008M to accept various logic standards, such as LVPECL, CML, LVDS, MN SUFFIX AWLYYWW LVCMOS or LVTTL logic levels. The V reference output can REFAC CASE 488AM be used to rebias capacitorcoupled differential or singleended input signals. The 1:8 fanout design was optimized for low output skew A = Assembly Location applications. The NB7L1008M is a member of the GigaComm WL = Wafer Lot family of high performance clock products. YY = Year WW = Work Week Features = PbFree Package Input Data Rate > 12 Gb/s Typical (Note: Microdot may be in either location) Data Dependent Jitter < 20 ps Maximum Input Clock Frequency > 8 GHz Typical SIMPLIFIED LOGIC DIAGRAM Random Clock Jitter < 0.8 ps RMS Low Skew 1:8 CML Outputs, < 25 ps max Q0 MultiLevel Inputs, accepts LVPECL, CML, LVDS Q0 160 ps Typical Propagation Delay Q1 45 ps Typical Rise and Fall Times Q1 Differential CML Outputs, 400 mV PeaktoPeak, Typical Operating Range: V = 2.375 V to 3.6 V, GND = 0 V Q2 CC Q2 Internal Input Termination Resistors, 50 V Reference Output REFAC Q3 IN QFN32 Package, 5 mm x 5 mm Q3 50 VT 40C to +85C Ambient Operating Temperature 50 Q4 IN These are PbFree Devices Q4 V REFAC Q5 Q5 Q6 Q6 Q7 Q7 ORDERING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: May, 2021 Rev. 2 NB7L1008M/DNB7L1008M Exposed Pad (EP) 32 31 30 29 28 27 26 25 VCC 1 24 GND 2 23 GND VCC Q3 22 3 IN VT 4 21 Q3 NB7L1008M 5 20 VREFAC Q4 IN 6 19 Q4 7 GND 18 VCC VCC 8 17 GND 9 10 11 12 13 14 15 16 Figure 1. 32 Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 3, 6 IN, IN LVPECL, CML, Noninverted / Inverted Differential Clock/Data Input. Note 1 LVDS Input 4 VT Internal 50 Termination Pin for IN and IN 2, 7 17,24 GND Negative Supply Voltage. (Note 2) 1, 8, 9, 16, 18, V Positive Supply Voltage. (Note 2) CC 23, 25, 32 31, 30, 29, 28, Q0, Q0, Q1, CML Noninverted / Inverted Differential Output. (Note 1) 27, 26, 22, 21, Q1, Q2, Q2, 20, 19, 15, 14, Q3, Q3, Q4, 13, 12, 11, 10 Q4, Q5, Q5, Q6, Q6, Q7, Q7 5 VREFAC Output Voltage Reference for CapacitorCoupled Inputs, only EP The Exposed Pad (EP) on the QFN24 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heatsinking conduit. The pad is electrically connected to GND and is recommended to be electrically connected to GND on the PC board. 1. In the differential configuration when the input termination pin (V ) is connected to a common termination voltage or left open, and if no signal T is applied on IN/IN, then the device will be susceptible to self oscillation. Qn/Qn outputs have internal 50 source termination resistors. 2. All V and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation. CC www.onsemi.com 2 VCC VCC Q0 Q7 Q0 Q7 Q6 Q1 Q6 Q1 Q5 Q2 Q5 Q2 VCC VCC