NB7VQ1006M 1.8 V / 2.5 V 10 Gbps Equalizer Receiver with 1:6 Differential CML Outputs Multi-Level Inputs W / Internal Termination www.onsemi.com Description The NB7VQ1006M is a high performance differential 1:6 CML fanout buffer with a selectable Equalizer receiver. When placed in series with a Data path operating up to 10 Gb/s, the NB7VQ1006M QFN24 will compensate the degraded data signal transmitted across a FR4 MN SUFFIX PCB backplane or cable interconnect and output six identical CML CASE 485L copies of the input signal. Therefore, the serial data rate is increased by reducing Inter-Symbol Interference (ISI) caused by losses in copper MARKING DIAGRAM* interconnect or long cables. The EQualizer ENable pin (EQEN) allows the IN/IN inputs to either 24 flow through or bypass the Equalizer section. Control of the Equalizer 1 NB7V function is realized by setting EQEN When EQEN is set Low, the Q1006M IN/IN inputs bypass the Equalizer. When EQEN is set High, the IN/IN ALYW inputs flow through the Equalizer. The default state at startup is LOW. As such, the NB7VQ1006M is ideal for SONET, GigE, Fiber Channel, A = Assembly Location Backplane and other Data distribution applications. L = Wafer Lot The differential inputs incorporate internal 50 termination Y = Year resistors that are accessed through the VT pin. This feature allows the W = Work Week NB7VQ1006M to accept various logic level standards, such as = Pb-Free Package LVPECL, CML or LVDS. This feature provides transmission line (Note: Microdot may be in either location) termination at the receiver, eliminating external components. The *For additional marking information, refer to Application Note AND8002/D. outputs have the flexibility of being powered by either a 1.8 V or 2.5 V supply. The NB7VQ1006M is a member of the GigaComm family of high SIMPLIFIED BLOCK DIAGRAM performance Clock/Data products. Features Maximum Input Data Rate > 10 Gbps Maximum Input Clock Frequency > 7.5 GHz EQ Backplane and Cable Interconnect Compensation 225 ps Typical Propagation Delay 30 ps Typical Rise and Fall Times Differential CML Outputs, 400 mV Peak-to-Peak, Typical Operating Range: V = 1.71 V to 2.625 V, GND = 0 V CC ORDERING INFORMATION Internal Input Termination Resistors, 50 Device Package Shipping QFN24 Package, 4 mm x 4 mm NB7VQ1006MMNG QFN24 92 Units / Tube 40C to +85C Ambient Operating Temperature (Pb-Free) This Device is Pb-Free, Halogen Free and is RoHS Compliant NB7VQ1006MMNTXG QFN24 3000 Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2016 Rev. 3 NB7VQ1006M/DNB7VQ1006M CML Outputs Q0 MultiLevel Inputs LVPECL, LVDS, CML Q0 Q1 IN 50 Q1 VT 0 Q2 50 IN Q2 Q3 EQ 1 Q3 Q4 Q4 EQEN (Equalizer Enable) 75 k Q5 Q5 Figure 1. Detailed Block Diagram of NB7VQ1006M Table 1. EQUALIZER ENABLE FUNCTION EQEN Function 0 IN/IN Inputs Bypass the EQualizer Section 1 IN/IN Inputs Flow through the EQualizer Section Exposed Pad (EP) 24 23 22 21 20 19 VCC 1 18 VCCO IN Q2 2 17 3 16 Q2 IN NB7VQ1006M 4 15 Q3 VT 5 14 EQEN Q3 6 13 VCCO VCC 78 9 10 11 12 Figure 2. QFN24 Lead Pinout (Top View) www.onsemi.com 2 GND GND Q5 Q0 Q0 Q5 Q1 Q4 Q4 Q1 GND GND