1.8 V/2.5 V/3.3 V 8 GHz/14 Gbps Differential 1:4 Clock/Data CML Fanout Buffer w/ Selectable Input Equalizer MultiLevel Inputs w/ Internal Termination www.onsemi.com MARKING NB7VQ14M DIAGRAM* 16 Description 1 The NB7VQ14M is a high performance differential 1:4 CML fanout 1 NB7V buffer with a selectable Equalizer receiver. When placed in series with QFN16 Q14M a Clock /Data path operating up to 8 GHz or 14 Gb/s, respectively, the MN SUFFIX ALYW NB7VQ14M inputs will compensate the degraded signal transmitted CASE 485G across a FR4 PCB backplane or cable interconnect and output four identical CML copies of the input signal with a 1.8 V, 2.5 V or 3.3 V A = Assembly Location power supply. Therefore, the serial data rate is increased by reducing L = Wafer Lot Inter Symbol Interference (ISI) caused by losses in copper Y = Year interconnect or long cables. The EQualizer ENable pin (EQEN) W = Work Week allows the IN/IN inputs to either flow through or bypass the Equalizer = PbFree Package section. Control of the Equalizer function is realized by setting EQEN (Note: Microdot may be in either location) When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When EQEN is set High, the IN/IN inputs flow through the Equalizer. The default state at startup is LOW. As such, NB7VQ14M is ideal for *For additional marking information, refer to Application Note AND8002/D. SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The differential inputs incorporate internal 50 termination SIMPLIFIED BLOCK DIAGRAM resistors that are accessed through the VT pin. This feature allows the NB7VQ14M to accept various logic level standards, such as LVPECL, CML or LVDS. The 1:4 fanout design was optimized for low output skew applications. The NB7VQ14M is a member of the GigaComm family of high EQ performance clock products. Features Input Data Rate > 14 Gb/s, Typical ORDERING INFORMATION Input Clock Frequency > 8 GHz, Typical See detailed ordering and shipping information in the package 165 ps Typical Propagation Delay dimensions section on page 9 of this data sheet. 30 ps Typical Rise and Fall Times < 15 ps Maximum Output Skew < 0.8 ps Maximum RMS Clock Jitter < 10 ps pp of Data Dependent Jitter Differential CML Outputs, 400 mV PeaktoPeak, Typical Selectable Input Equalization Operating Range: V = 1.71 V to 3.6 V with GND = 0 V CC Internal Input Termination Resistors, 50 40C to +85C Ambient Operating Temperature These are PbFree Devices Semiconductor Components Industries, LLC, 2010 1 Publication Order Number: May, 2021 Rev. 1 NB7VQ14M/DNB7VQ14M MultiLevel Inputs LVPECL, LVDS, CML CML Outputs Q0 IN 50 Q0 VT 0 Q1 50 IN Q1 2:1 MUX Q2 VREFAC EQ 1 V Q2 CC GND Q3 Q3 EQEN (Equalizer Enable) 75 k Figure 1. Detailed Block Diagram of NB7VQ14M GND Q0 Q0 V Exposed Pad (EP) CC Table 1. EQUALIZER ENABLE FUNCTION 16 15 14 13 EQEN Function 0 IN / IN Inputs Bypass the Equalizer section IN 1 12 Q1 1 Inputs flow through the Equalizer VT 2 11 Q1 NB7VQ14M VREFAC 3 10 Q2 IN 4 9 Q2 56 7 8 EQEN Q3 Q3 V CC Figure 2. QFN16 Pinout (Top View) www.onsemi.com 2