NB7VQ58M 1.8V / 2.5V / 3.3V Differential 2:1 Clock/Data Multiplexer / Translator with CML Outputs NB7VQ58M MultiLevel Inputs LVPECL, LVDS, CML Exposed VT0 GND GND VCC Pad (EP) IN0 50 16 15 14 13 0 VT0 50 IN0 1 12 Q 0 IN0 2:1 Mux IN0 2 11 IN1 GND NB7VQ58M 50 Q 1 2:1 IN1 3 10 GND VT1 Mux Q 50 V CC IN1 4 9 Q IN1 1 EQ 75 k SEL 56 7 8 EQEN VT1 SEL EQEN VCC (Equalizier Enable) 75 k VCC GND Figure 1. Pin Configuration (Top View) Figure 2. Detailed Block Diagram Table 1. EQualizer ENable FUNCTION Table 2. SELect FUNCTION TRUTH TABLE EQEN Function SEL Q Q 0 INn / INn Inputs Bypass the EQualizer section L D0 D0 1 Inputs flow through the EQualizer H D1 D1 Table 3. PIN DESCRIPTION Pin Name I/O Description 1 IN0 LVPECL, CML, LVDS Input Noninverted Differential Input (Note 1) 2 IN0 LVPECL, CML, LVDS Input Inverted Differential Input (Note 1) 3 IN1 LVPECL, CML, LVDS Input Noninverted Differential Input (Note 1) 4 IN1 LVPECL, CML, LVDS Input Inverted Differential Input (Note 1) 5 VT1 Internal 50 Termination Pin for IN1/IN1 6 SEL LVTTL/LVCMOS Input SEL Input. Low for IN0 inputs, High for IN1 inputs. (Note 1) Pin will default HIGH when left open (has internal pullup resistor) 7 EQEN LVCMOS Input Equalizer Enable Input pin will default LOW when left open (has internal pulldown resistor) 8 VCC Positive Supply Voltage (Note 2) 9 Q CML Output Inverted Differential Output 10 GND Negative Supply Voltage 11 GND Negative Supply Voltage 12 Q CML Output Noninverted Differential Output 13 VCC Positive Supply Voltage (Note 2) 14 GND Negative Supply Voltage 15 GND Negative Supply Voltage 16 VT0 Internal 50 Termination Pin for IN0/IN0 EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heatsinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on IN0/IN0, IN1/IN1 inputs, then the device will be susceptible to selfoscillation. Q/Q outputs have internal 50 source termination resistors. 2. All VCC and GND pins must be externally connected to a power supply for proper operation.