NBA3N206SDR2G ON Semiconductor

NBA3N206S 3.3 V Automotive Grade M-LVDS Driver Receiver Description The NBA3N206S is a 3.3 V supply differential Multipoint Low Voltage (MLVDS) line Driver and Receiver for automotive www.onsemi.com applications. NBA3N206S offers the Type 2 receiver threshold at 0.1 V. MARKING DIAGRAM The NBA3N206S has Type2 receivers that detect the bus state with as little as 50 mV of differential input voltage over a commonmode 8 voltage range of 1 V to 3.4 V. Type2 receivers include an offset SOIC8 NA206 8 D SUFFIX AYWW threshold to provide a detectable voltage under opencircuit, idlebus, 1 CASE 751 and other faults conditions. 1 NBA3N206S supports Simplex or Half Duplex bus configurations. NA206 = Specific Device Code Features A = Assembly Location LowVoltage Differential 30 to 55 Line Drivers and Receivers Y = Year WW = Work Week for Signaling Rates Up to 200 Mbps G or = PbFree Package Type2 Receivers Provide an Offset (100 mV) Threshold to Detect OpenCircuit and IdleBus Conditions Controlled Driver Output Voltage Transition Times for Improved ORDERING INFORMATION Signal Quality See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. 1 V to 3.4 V CommonMode Voltage Range Allows Data Transfer With up to 2 V of Ground Noise Bus Pins High Impedance When Disabled or VCC 1.5 V MLVDS Bus Power Up/Down Glitch Free Operating range: VCC = 3.3 10% V( 3.0 to 3.6 V) Operation from 40C to +125C. AECQ100 Qualified and PPAP Capable These are PbFree Devices Applications LowPower HighSpeed ShortReach Alternative to TIA/EIA485 Backplane or Cabled Multipoint Data and Clock Transmission Cellular Base Stations CentralOffice Switches Network Switches and Routers Automotive Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: October, 2015 Rev. 3 NBA3N206S/DNBA3N206S R 1 8 V CC RE B 2 7 DE 3 A 6 4 D GND 5 SOIC8 Figure 1. Logic Diagram Figure 2. Pinout Diagram (Top View) Table 1. PIN DESCRIPTION Number Name I/O Type Open Default Description 1 R LVCMOS Output Receiver Output Pin 2 RE LVCMOS Input High Receiver Enable Input Pin (LOW = Active, HIGH = High Z Output) 3 DE LVCMOS Input Low Driver Enable Input Pin (LOW = High Z Output, HIGH=Active) 4 D LVCMOS Input Driver Input Pin 5 GND Ground Supply pin. Pin must be connected to power supply to guarantee proper operation. 6 A MLVDS Input Transceiver True Input /Output Pin /Output 7 B MLVDS Input Transceiver Invert Input /Output Pin /Output 8 VCC Power Supply pin. Pin must be connected to power supply to guarantee proper operation. Table 2. DEVICE FUNCTION TABLE Inputs Output V = V V RE R ID A B V 150 mV L H ID 50 mV < V < 150 mV L ID TYPE 2 Receiver V 50 mV L L ID X H Z X Open Z Open L L Input Enable Output D DE A / Y B / Z L H L H H H H L DRIVER Open H L H X Open Z Z X L Z Z H = High, L = Low, Z = High Impedance, X = Dont Care, = Indeterminate www.onsemi.com 2