NBSG11MNG ON Semiconductor

NBSG11 2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Outputs *Reduced Swing ECL NBSG11 V NC NC V EE CC Exposed Pad (EP) 16 15 14 13 VTCLK 1 12 Q0 CLK 2 11 Q0 NBSG11 Q1 CLK 3 10 VTCLK Q1 4 9 56 7 8 V NC NC V EE CC Figure 1. QFN16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VTCLK Internal 50 Termination Pin. See Table 2. 2 CLK ECL, CML, Inverted Differential Input. Internal 75 k to V and 36.5 k to V . EE CC LVCMOS, LVDS, LVTTL Input 3 CLK ECL, CML, Noninverted Differential Input. Internal 75 k to V . EE LVCMOS, LVDS, LVTTL Input 4 VTCLK Internal 50 Termination Pin. See Table 2. 5,16 V Negative Supply Voltage EE 6,7,14,15 NC No Connect 8,13 V Positive Supply Voltage CC 9 Q1 RSECL Output Inverted Differential Output 1. Typically Terminated with 50 to V = V 2.0 V. TT CC 10 Q1 RSECL Output Noninverted Differential Output 1. Typically Terminated with 50 to V = V 2.0 V. TT CC 11 Q0 RSECL Output Inverted Differential output 0. Typically Terminated with 50 to V = V 2.0 V. TT CC 12 Q0 RSECL Output Noninverted Differential Output 0. Typically Terminated with 50 to V = V 2.0 V. TT CC EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat sinking conduit. The pad is not electrically connected to the die but may be electrically and thermally connected to V on the PC board. EE 1. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package CC EE bottom (see case drawing) must be attached to a heatsinking conduit. 2. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to selfoscillation.