NBSG16 2.5 V/3.3 VSiGe Differential Receiver/Driver with RSECL* Outputs *Reduced Swing ECL NBSG16 V V V V EE BB MM EE Exposed Pad (EP) 16 15 14 13 VTD 1 12 V CC D 2 11 Q NBSG16 D Q 3 10 VTD V 4 9 CC 56 7 8 V NC NC V EE EE Figure 1. QFN16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VTD Internal 50 Termination Pin. See Table 2. 2 D ECL, CML, Inverted Differential Input. Internal 75 k to V and 36.5 k to V . EE CC LVCMOS, LVDS, LVTTL Input 3 D ECL, CML, Noninverted differential input. Internal 75 k to V EE LVCMOS, LVDS, LVTTL Input 4 VTD Internal 50 Termination Pin. See Table 2. 5, 8, V Negative Supply Voltage EE 13, 16 6,7 NC No Connect 9, 12 V Positive Supply Voltage CC 10 Q RSECL Output Noninverted Differential Output. Typically Terminated with 50 to V = V 2 V TT CC 11 Q RSECL Output Inverted Differential Output. Typically Terminated with 50 to V = V 2 V TT CC 14 V LVCMOS Reference Voltage Output. (V V )/2 MM CC EE 15 V ECL Reference Voltage Output BB EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die but may be electrically and thermally connected to V on the PC board. EE 1. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package CC EE bottom (see case drawing) must be attached to a heat-sinking conduit. 2. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation.