TinyLogic UHS Triple Buffer with Schmitt Trigger Inputs NC7NZ17 Description The NC7NZ17 is a triple buffer with Schmitt trigger inputs from ON Semiconductorss Ultra High Speed Series of TinyLogic in the www.onsemi.com US8 package. The device is fabricated with advanced CMOS technology to achieve ultra high speed with high output drive while MARKING maintaining low static power dissipation over a very broad V CC DIAGRAMS operating range. The device is specified to operate over the 1.65 V to 5.5 V V range. The inputs and outputs are high impedance when CC UQFN8 U4KK V is 0 V. Inputs tolerate voltages up to 5.5 V independent of V CC CC 1.6X1.6, 0.5P XYZ operating voltage. Schmitt trigger inputs typically achieve 1 V CASE 523AY hysteresis between the positive going and negative going input threshold voltage at 5 V V . CC Features Space Saving US8 Surface Mount Package NZ17 US8 ALYW MicroPak PbFree Leadless Package CASE 846AN Ultra High Speed: t 3.6 ns Typ into 50 pF at 5 V V PD CC High Output Drive: 24 mA at 3 V V CC Broad V Operating Range: 1.65 V to 5.5 V CC Power Down High Impedance Inputs / Outputs U4, NZ17 = Specific Device Code Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation KK = 2Digit Lot Run Traceability Code XY = 2Digit Date Code Format Proprietary Noise / EMI Reduction Circuitry Implemented Z = Assembly Plant Code These Devices are PbFree, Halogen Free/BFR Free and are RoHS A = Assembly Site L = Wafer Lot Number Compliant YW = Assembly Start Week IEEE / IEC (1) (7) 1A 1Y ORDERING INFORMATION See detailed ordering, marking and shipping information in the (3) (5) package dimensions section on page 6 of this data sheet. 2A 2Y (6) (2) 3A 3Y Figure 1. Logic Symbol Semiconductor Components Industries, LLC, 2005 1 Publication Order Number: October, 2020 Rev. 2 NC7NZ17/DNC7NZ17 Connection Diagrams V 1Y 3A 2Y CC 87 6 5 1A 3Y 2A 7 6 5 V 8 4 GND CC 12 3 4 1 2 3 1A 3Y 2A GND 1Y 3A 2Y Figure 2. Connection Diagram (Top View) Figure 4. Pad Assignments for MicroPak (Top Thru View) AAA (Top View) Pin One AAA represents Product Code Top Mark see ordering code NOTE: Orientation of Top Mark determines Pin One location. Read the Top Product Code Mark left to right, Pin One is the lower left pin (see diagram). Figure 3. Pin One Orientation Diagram PIN DESCRIPTIONS FUNCTION TABLE (Y = A) Name Description Input Output A , A , A Data Inputs A Y 1 2 3 Y , Y , Y Output L L 1 2 3 H H H = HIGH Logic Level L = LOW Logic Level www.onsemi.com 2