DATA SHEET www.onsemi.com Bluetooth 5.2 Radio System-on-Chip (SoC) WLCSP51 CASE 567MT RSL10 Introduction RSL10 is an ultralowpower, highly flexible multiprotocol 1 48 2.4GHz radio specifically designed for use in highperformance QFN48 wearable and medical applications. With its Arm Cortex M3 CASE 485BA Processor and LPDSP32 DSP core, RSL10 supports Bluetooth Low Energy technology and 2.4 GHz proprietary protocol stacks, without sacrificing power consumption. Key Features RSL10 RSL10 Rx Sensitivity (Bluetooth Low Energy Mode, 1 Mbps): 94 dBm AWLYWW AWLYYWWG Data Rate: 62.5 to 2000 kbps Transmitting Power: 17 to +6 dBm (QFN48) (WLCSP51) Peak Rx Current = 5.6 mA (1.25 V VBAT) XXXXXX = Specific Device Code Peak Rx Current = 3.0 mA (3 V VBAT) A = Assembly Location Peak Tx Current (0 dBm) = 8.9 mA (1.25 V VBAT) WL = Wafer Lot Y or YY = Year Peak Tx Current (0 dBm) = 4.6 mA (3 V VBAT) WW = Work Week Bluetooth 5.2 Certified with LE 2Mbit PHY (High Speed), G or = PbFree Package as well as Backwards Compatibility and Support for Earlier Bluetooth Low Energy Specifications Arm CortexM3 Processor Clocked at up to 48 MHz ORDERING INFORMATION LPDSP32 for Audio Codec Device Package Shipping Supply Voltage Range: 1.1 3.3 V NCHRSL10 WLCSP51 5000 / Current Consumption (1.25 V VBAT): 101WC51ABG (PbFree) Tape & Reel Deep Sleep, IO Wakeup: 50 nA NCHRSL10 QFN48 3000 / Deep Sleep, 8 kB RAM Retention: 300 nA 101Q48ABG (PbFree) Tape & Reel Audio Streaming at 7 kHz Audio BW: 1.8 mA RX, 1.8 mA TX For information on tape and reel specifications, Current Consumption (3 V VBAT): including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Deep Sleep, IO Wakeup: 25 nA Brochure, BRD8011/D. Deep Sleep, 8 kB RAM Retention: 100 nA Audio Streaming at 7 kHz Audio BW: 0.9 mA RX, 0.9 mA TX 384 kB of Flash Memory Highlyintegrated SystemonChip (SoC) Supports FOTA (Firmware OverTheAir) Updates Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: January, 2022 Rev. 7 RSL10/DRSL10 FEATURES Arm CortexM3 Processor: A 32bit core for realtime Flexible Supply Voltage: RSL10 integrates high applications, specifically developed to enable efficiency power regulators and has a VBAT range of 1.1 highperformance lowcost platforms for a broad range to 3.3 V. See Table 2. RECOMMENDED OPERATING of lowpower applications. CONDITIONS. 2 LPDSP32: A 32 bit Dual Harvard DSP core that Highly Configurable Interfaces: I C, UART, two SPI efficiently supports audio codecs required for wireless interfaces, PCM interface, multiple GPIOs. It also audio communication. Various codecs are available to supports a digital microphone interface (DMIC) and an customers through libraries that are included in RSL10s output driver (OD). development tools. The Asynchronous Sample Rate Converter (ASRC) Radio Frequency FrontEnd: Based on a 2.4 GHz RF Block and Audio Sink Clock Blocks: Provides a means transceiver, the RFFE implements the physical layer of of synchronizing the audio sample rate between an audio the Bluetooth Low Energy technology standard and other source and an audio sink. The audio sink clock also proprietary or custom protocols. provides a high accuracy mechanism to measure an input clock used for the RTC or protocol timing. Protocol Baseband Hardware: Bluetooth 5.2 certified and includes support for a 2 Mbps RF link and custom Flexible Clocking Scheme: RSL10 must be clocked protocol options. The RSL10 baseband stack is from the XTAL/PLL of the radio frontend at 48 MHz supplemented by support structures that enable when transmitting or receiving RF traffic. When RSL10 implementation of onsemi and customer designed is not transmitting/receiving RF traffic, it can run off the custom protocols. 48 MHz XTAL, the internal RC oscillators, the 32 kHz oscillator, or an external clock. A low frequency RTC HighlyIntegrated SoC: The dualcore architecture is clock at 32 kHz can also be used in Deep Sleep Mode. It complemented by highefficiency power management can be sourced from either the internal XTAL, the RC units, oscillators, flash and RAM memories, a DMA oscillator, or a digital input pad. controller, along with a full complement of peripherals Diverse Memory Architecture: 76kB of SRAM and interfaces. program memory (4 kB of which is PROM containing the Deep Sleep Mode: RSL10 can be put into a Deep Sleep chip bootup program, and is thus unavailable to the user) Mode when no operations are required. Various Deep and 88 kB of SRAM data memory are available. A total Sleep Mode configurations are available, including: of 384 kB of flash is available to store the Bluetooth stack IO wakeup configuration. The power consumption and other applications. The Arm CortexM3 processor in deep sleep mode is 50 nA (1.25 V VBAT). can execute from SRAM and/or flash. Embedded 32 kHz oscillator running with interrupts Security: AES128 encryption hardware block for custom from timer or external pin. The total current drain is 90 nA (1.25 V VBAT). secure algorithms and code protection with authenticated As above with 8 kB RAM data retention. The total debug port access (JTAG lock) current drain is 300 nA (1.25 V VBAT). UltraLow Power Consumption Application The DCDC converter can be used in buck mode or Examples: LDO mode during Sleep Mode, depending on VBAT Audio Signal Streaming: IDD = 1.8 mA VBAT voltage. 1.25V in Rx Mode for receiving, decoding and Standby Mode: Can be used to reduce the average power sending an 7 kHz bandwidth audio signal to the SPI consumption for offduty cycle operation, ranging interface using a proprietary custom audio protocol typically from a few ms to a few hundreds of ms. The from onsemi. typical chip power consumption is 30 A in Standby Low Duty Cycle Advertising: IDD 1.1 A for Mode. advertising at all three channels at 5 second intervals VBAT 3 V, DCDC converter enabled. MultiProtocol Support: Using the flexibility provided RoHS Compliant Device by LPDSP32, the Arm CortexM3 processor, and the RF frontend proprietary protocols and other custom protocols are supported. www.onsemi.com 2