Low Quiescent Current, Programmable Delay Time, Supervisory Circuit NCP308, NCV308 The NCP308 series is one of the ON Semiconductor Supervisory circuit IC families. It is optimized to monitor system voltages from www.onsemi.com 0.405 V to 5.5 V, asserting an active low opendrain RESET output, MARKING together with Manual Reset (MR) Input. The part comes with both DIAGRAMS fixed and externally adjustable versions. Features TSOP6 Wide Supply Voltage Range 1.6 to 5.5 V XXXAYW CASE 318G Very Low Quiescent Current 1.6 A 1 1 Fixed Threshold Voltage Versions for Standard Voltage Rails Including 0.9 V, 1.2 V, 1.25 V, 1.5 V, 1.8 V, 1.9 V, 2.5 V, 2.8 V, 3.0 V, 1 3.3 V, 5.0 V WDFN6 XX M CASE 511BR Adjustable Version with Low Threshold Voltage 0.405 V (min) High Threshold Voltage Accuracy: 0.31% typ Support Manual Reset Input ( MR) XXX, XX= Specific Device Code OpenDrain RESET Output (Pushpull Output upon Request) A =Assembly Location Flexible Delay Time Programmability: 1.25 ms to 10 s Y = Year W = Work Week Temperature Range: 40C to +125C M = Date Code Small TSOP6 and WDFN6 2 x 2 mm, PbFree packages = PbFree Package NCV Prefix for Automotive and Other Applications Requiring (Note: Microdot may be in either location) Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable ORDERING INFORMATION These are PbFree Devices See detailed ordering and shipping information in the ordering information section on page 9 of this data sheet. Typical Applications DSP or Microcontroller Applications Notebook/Desktop Computers PDAs/HandHeld Products Portable/BatteryPowered Products FPGA/ASIC Applications VIN VDD VIN VDD NCP308XXADJ Rpullup Rpullup RESET RESET RESET RESET VDD VDD DSP/ DSP/ R1 Processor Processor SENSE CT SENSE CT CT CT 1 nF R2 MR MR (Optional) (Optional) (Optional) MR GND MR GND Figure 1. Typical Application Circuit for Adjustable Figure 2. Typical Application Circuit for Fixed Versions Versions Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: December, 2020 Rev. 9 NCP308/DNCP308, NCV308 VDD VDD VDD NCP308SNADJ/NCP308MTADJ VDD NCP308SNXXX/NCP308MTXXX Adjustable Versions Fixed Versions CT 90k CT 90k MR MR RESET RESET SENSE SENSE Control Logic Control Logic and Timer and Timer + + R1 Vref Vref R2 Figure 3. Functional Block Diagrams of Adjustable and Fixed Versions RESET 1 6 VDD VDD 1 6 RESET GND 2 5 SENSE 2 5 GND SENSE 3 MR 4 CT 3 CT 4 MR Figure 4. Pin Connections Diagram (Top View) Table 1. PIN OUT DESCRIPTION Pin Number TSOP6 WDFN6 Name Description VDD 6 1 Supply Voltage. A 0.1uF ceramic capacitor placed close to this pin is helpful for transient and parasitic. SENSE 5 2 Sense Input, this is the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage V , then RESET is asserted. SENSE does not necessary monitor VDD, it can IT monitor any voltage lower than VDD. CT 4 3 Reset Delay Time Setting Pin. Connecting this pin to VDD through a 40 k to 200 k resistor or leaving it open results in fixed reset delay times. Connecting this pin to a ground referenced capacitor ( 100 pF) gives a userprogrammable reset delay time. See the Setting Reset Delay Time section for more information. MR 3 4 Manual Reset input, MR low asserts RESET. MR is internally tied to VDD by a 90 k pullup Resistor. RESET 1 6 RESET Output, is an Active low open drain NChannel MOSFET output, it is driven to a low impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (V ) or the MR pin is set to a logic low). RESET will keep low (asserted) for the reset IT delay time after both SENSE is above V and MR is set to a logic high. A pullup resistor from IT 10k to 1M should be used on this pin. See Figure 5 for behavior of RESET depends on VDD, SENSE and MR conditions. GND 2 5 Ground terminal. Should be connected to PCB ground reference EXP Exposed Exposed pad, under WDFN6 package, connect it to ground plane for better thermal dissipation. PAD Pad www.onsemi.com 2 GND GND