NCP3135MNTXG ON Semiconductor

NCP3135 Integrated Synchronous Buck Converter 5 A NCP3135 is a fully integrated synchronous buck converter for 3.3 V www.onsemi.com and 5 V stepdown applications. It can provide up to 5 A DC load and 6 A instantaneous load current. NCP3135 supports high efficiency, fast transient response and provides power good indicator. The control scheme includes two operation modes: FCCM and automatic 1 CCM/DCM. In automatic CCM/DCM mode, the controller can QFN16 3 x 3, 0.5P smoothly switch between CCM and DCM, where converter runs at CASE 485DA reduced switching frequency with much higher efficiency. NCP3135 is available in 3 mm x 3 mm QFN16 pin package. SUGGESTED PIN ARRANGEMENT Features PGND PGND VIN VIN High Efficiency in both CCM and DCM 16 15 14 13 High Operation Frequency at 1.1 MHz Support MLCC Output Capacitor EN VDD 1 12 Small Footprint, 3 mm x 3 mm, 16pin QFN Package NC AGND Up to 5 A Continuous Output Current 2 11 NCP3135 6 A Instantaneous Load Current PGD 10 FB 3 2.9 V to 5.5 V Wide Conversion Voltage Range Output Voltage Range from 0.6 V to 0.84 X Vin VBST 4 9 COMP Internal 1 ms SoftStart 5 67 8 Automatic PowerSaving Mode SW SW SW PS Voltage Mode Control Support Pre-bias Startup Functionality MARKING DIAGRAM Output Discharge Operation OverTemperature Protection 3135 Builtin OverVoltage, UnderVoltage and Over-Current Protection ALYW Power Good Indicator This is a PbFree Device 3135 = Specific Device Code Applications A = Assembly Location L = Wafer Lot 5 V Step Down Rail Y = Year 3.3 V Step Down Rail W = Work Week = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 12 of this data sheet. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: August, 2019 Rev. 1 NCP3135/DNCP3135 VIN VBST UVLO OSC NC Ramp Control Logic DRVH & PS PWM Logic SS EN SW COMP VREF + DRVL +E/A Power Good, FB PGND UVP, OVP, UVLO, Overtemperature OCP PGD and Vout discharge UVLO VDD AGND Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin No. Symbol Description 1 EN Logic control to enabling the switcher. Internally pulled up to VDD with a 1.35 M resistor 2 NC Not connected 3 PGD Open drain power good output 4 VBST Gate drive voltage for high side FET. Connect capacitor from this pin to SW 5, 6, 7 SW Switch node between highside MOSFET and lowside MOSFET 8 PS Mode configuration pin (with 10 A current): Pulled high or floating (internally pulled high): Forced Continuous Conduction Mode Connect with resistor equal to or lower than ()174 k to GND: Automatic CCM/DCM 9 COMP Output of the error amplifier 10 FB Feedback pin. Connect to resistor divider to set up the desired output voltage 11 AGND Analog ground 12 VDD Power supply input for control circuitry 13, 14 VIN Power input for power conversion and gate driver supply 15, 16 PGND Power ground www.onsemi.com 2