NCP81151MNTAG ON Semiconductor

NCP81151 MOSFET Driver, VR12.5 Compatible Synchronous Buck The NCP81151 is a high performance dual MOSFET gate driver www.onsemi.com optimized to drive the gates of both highside and lowside power MOSFETs in a synchronous buck converter. It can drive up to 3 nF load with a 25 ns propagation delay and 20 ns transition time. MARKING Adaptive anticrossconduction and power saving operation circuit DIAGRAM can provide a low switching loss and high efficiency solution for 1 1 notebook systems. A3M DFN8 The UVLO function guarantees the outputs are low when the supply CASE 506AA voltage is low. Features A3 = Specific Device Code M = Date Code Faster Rise and Fall Times = PbFree Package Adaptive AntiCrossConduction Circuit (Note: Microdot may be in either location) Zero Cross Detection function Output Disable Control Turns Off Both MOSFETs PINOUT DIAGRAM Undervoltage Lockout Power Saving Operation Under Light Load Conditions BST 1 8 DRVH Direct Interface to NCP6131 and Other Compatible PWM Controllers SW PWM 2 7 FLAG Thermally Enhanced Package 9 EN 3 6 GND These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant VCC 4 DRVL 5 Typical Applications Power Management Solutions for Notebook Systems ORDERING INFORMATION Device Package Shipping NCP81151MNTAG DFN8 3000 / Tape & (PbFree) Reel NCP81151MNTBG DFN8 3000 / Tape & (PbFree) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: April, 2015 Rev. 4 NCP81151/DNCP81151 BST VCC DRVH PWM Logic SW AntiCross Conduction VCC DRVL EN ZCD Detection UVLO Figure 1. Block Diagram PIN DESCRIPTIONS Pin No. Symbol Description 1 BST Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and the SW pin. 2 PWM Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode Emulation Enabled, High = High Side FET Enabled. 3 EN Logic input. A logic high to enable the part and a logic low to disable the part. Three states logic input: EN = High to enable the gate driver EN = Low to disable the driver EN = Mid to go into diode mode (both high and low side gate drive signals are low) 4 VCC Power supply input. Connect a bypass capacitor (0.1 F) from this pin to ground. 5 DRVL Low side gate drive output. Connect to the gate of low side MOSFET. 6 GND Bias and reference ground. All signals are referenced to this node. 7 SW Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET. 8 DRVH High side gate drive output. Connect to the gate of high side MOSFET. 9 FLAG Thermal flag. There is no electrical connection to the IC. Connect to ground plane. www.onsemi.com 2