NCP81155MNTXG ON Semiconductor

NCP81155 MOSFET Driver The NCP81155 is a highperformance dual MOSFET gate driver in a small 3 mm x 3 mm package, optimized to drive the gates of both highside and lowside power MOSFETs in a buck or buckboost application. VCC UVLO ensures the MOSFETs are off when supply voltages are low. A bidirectional Enable pin provides a fault signal www.onsemi.com to the controller when a UVLO fault is detected. Features SpaceEfficient 3 mm x 3 mm DFN8 ThermallyEnhanced Package 1 VCC Range of 4.5 V to 13.2 V DFN8 MN SUFFIX Integrated Bootstrap Diode CASE 506BJ Compatible with 3.3 V and 5 V PWM Inputs BiDirectional Enable Feature Pulls Enable Pin low during a UVLO Fault. MARKING DIAGRAM Adaptive AntiCross Conduction Circuit Protects against 1 Cross Conduction during FET Turnon and Turnoff 81155 Output Disable Control Turns Off Both MOSFETs ALYW VCC Undervoltage Lockout These Devices are PbFree, Halogen Free/BFR Free and are RoHS 81155 = Specific Device Code Compliant A = Assembly Location L = Wafer Lot Typical Applications Y = Year ECigarettes W = Work Week = PbFree Package Unmanned Aerial Vehicles (UAV) (Note: Microdot may be in either location) PIN CONNECTIONS 1 8 BST DRVH PWM27 SW FLAG 9 36 EN GND 45 VCC DRVL (Top View) ORDERING INFORMATION Device Package Shipping NCP81155MNTXG DFN8 3000 / Tape & Reel (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: January, 2019 Rev. 0 NCP81155/DNCP81155 BST VCC DRVH PWM Logic SW AntiCross Conduction VCC DRVL EN UVLO VCC Fault Figure 1. Simplified Block Diagram Table 1. Pin Descriptions Pin No. Symbol Description 1 BST Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and the SW pin. 2 PWM Control input: PWM = High DRVH is high, DRVL is low. PWM = Low DRVH is low, DRVL is high. 3 EN Enable input: EN = High Driver is enabled. EN = Low Driver is disabled. 4 VCC Power supply input. Connect a bypass capacitor (0.1 F) from this pin to ground. 5 DRVL Low side gate drive output. Connect to the gate of low side MOSFET. 6 GND Bias and reference ground. All signals are referenced to this node (QFN Flag). 7 SW Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET. 8 DRVH High side gate drive output. Connect to the gate of high side MOSFET. 9 FLAG Thermal flag. There is no electrical connection to the IC. Connect to ground plane. www.onsemi.com 2