NCP51199, NCV51199 DDR 2-Amp Source / Sink V Termination Regulator TT The NCP/NCV51199 is a linear regulator designed to supply a regulated V termination voltage for DDR2 and DDR3 memory TT applications. The regulator is capable of actively sourcing and sinking www.onsemi.com 2 A peak currents for DDR2, and DDR3 up to 1.5 A while regulating the V output voltage to within 10 mV. The output TT MARKING termination voltage is regulated to track V / 2 by two external DDQ DIAGRAM voltage divider resistors connected to the PV , GND, and V pins. CC REF 8 The NCP/NCV51199 incorporates a highspeed differential amplifier to provide ultrafast response to line and load transients. XXXXXX SOIC8NB EP Other features include source/sink current limiting, softstart and ALYW 8 PD SUFFIX onchip thermal shutdown protection. CASE 751BU 1 1 Features Supports DDR2 V Termination to 2 A, DDR3 to 1.5 A (peak) TT XXXXXX = Specific Device Code A = Assembly Location Stable with 10 F Ceramic Capacitance on V Output TT L = Wafer Lot Integrated Power MOSFETs Y = Year High Accuracy V Output at FullLoad WW = Work Week TT = PbFree Package Fast Transient Response Builtin SoftStart Shutdown for Standby or Suspend Mode PIN CONNECTION Integrated Thermal and CurrentLimit Protection 18 NCV Prefix for Automotive and Other Applications Requiring PVCC NC Unique Site and Control Change Requirements AECQ100 GND NC Qualified and PPAP Capable VREF V CC These Devices are PbFree and are RoHS Compliant V NC TT SOIC8 EP Typical Applications SDRAM Termination Voltage for DDR2 / DDR3 ORDERING INFORMATION Motherboard, Notebook, and VGA Card Memory Termination See detailed ordering, marking and shipping information in the Set Top Box, Digital TV, Printers package dimensions section on page 6 of this data sheet. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: April, 2017 Rev. 3 NCP51199/DNCP51199, NCV51199 NCP51199 PV = 1.5 to 5.0 V* CC 1 5 V 6 PV CC V CC C2 C3 R2 2 100k GND 3 V = 0.75 to 2.5 V* TT V 4 REF V TT C1 R1 Enable C4 100k R3 *For DDR2: PV = 1.8 V, V = 0.9 V CC TT DDR3: PV = 1.5 V, V = 0.75 V CC TT C1 = 1 F (Low ESR) C4 = 1000 F + 10 F (10 F ceramic) C2 = 470 F (Low ESR) R3 = Optional V discharge resistor TT C3 = 47 F Nch MOSFET = Optional Enable / Disable Figure 1. Application Diagram PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1 PV Input voltage which supplies current to the output pin. C = 470 F with low ESR. CC IN 2 GND Common Ground 3 V Buffered reference voltage input equal to of V and active low shutdown pin. An external resistor REF DDQ divider dividing down the PV voltage creates the regulated output voltage. Pulling the pin to ground CC (0.15 V maximum) turns the device off. 4 V Regulator output voltage capable of sourcing and sinking current while regulating the output rail. TT C = 1000 F + 10 F ceramic with low ESR. OUT 5 NC True No Connect 6 V The V pin is a 5 V input pin that provides internal bias to the controller. PV should always be kept CC CC CC lower or equal to V . CC 7 NC True No Connect 8 NC True No Connect EP Thermal Pad Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple vias for maximum power dissipation performance. www.onsemi.com 2