NCV7329 Stand-alone LIN Transceiver Description The NCV7329 is a fully featured local interconnect network (LIN) transceiver designed to interface between a LIN protocol controller and the physical bus. The LIN bus is designed to communicate low rate data from control www.onsemi.com devices such as door locks, mirrors, car seats, and sunroofs at the lowest possible cost. The bus is designed to eliminate as much wiring MARKING as possible and is implemented using a single wire in each node. Each DIAGRAMS node has a slave MCUstate machine that recognizes and translates 8 the instructions specific to that function. SOIC8 The main attraction of the LIN bus is that all the functions are not NV7329 8 CASE 751AZ ALYW time critical and usually relate to passenger comfort. 1 Features 1 LINBus Transceiver 1 NV73 Compliant to ISO 179874 (Backwards Compatible to LIN DFN8 29 Specification rev. 2.x, 1.3) and SAE J2602 CASE 507AB ALYW 1 Bus Voltage 42 V Transmission Rate 1 kbps to 20 kbps A = Assembly Location TxD Timeout Function L = Wafer Lot Integrated Slope Control Y = Year Protection W = Work Week Thermal Shutdown = PbFree Package Undervoltage Protection (Note: Microdot may be in either location) Bus Pins Protected Against Transients in an Automotive Environment PIN CONNECTIONS Modes 1 8 RxD NC Normal Mode: LIN Transceiver Enabled, Communication via the 2 7 V Bus is Possible EN BB 3 6 Sleep Mode: LIN Transceiver Disabled, the Consumption from NC LIN 4 5 V is Minimized BB TxD GND Standby Mode: Transition Mode Reached after Wakeup Event on SOIC8 (Top View) the LIN Bus Compatibility RxD 1 8 NC PinCompatible Subset with NCV7321 EN 2 7 V BB Kline Compatible EP NC 3 6 LIN Quality TxD 4 5 GND NCV Prefix for Automotive and Other Applications Requiring DFN8 (Top View) Unique Site and Control Change Require ments AECQ100 Qualified and PPAP Capable ORDERING INFORMATION These Devices are PbFree, Halogen Free/BFR Free and are RoHS See detailed ordering and shipping information on page 10 of this data sheet. Compliant Semiconductor Components Industries, LLC, 2018 1 Publication Order Number: May, 2018 Rev. 0 NCV7329/DNCV7329 BLOCK DIAGRAM V BB POR I sleep EN State Thermal shutdown Control D S Osc R SLAVE COMP + RxD Filter LIN TxD timeout Slope Control NCV7329 GND Figure 1. Block Diagram TYPICAL APPLICATION Slave Node Master Node bat bat VBAT VBAT 3.3/5V 3.3/5V V V BB BB VCC VCC 7 RxD 7 RxD 8 8 1 1 LIN LIN TxD LIN LIN TxD 6 4 6 4 EN EN 3 2 3 2 5 5 GND GND GND GND GND GND LB20140619.0 LB20140619.0 KL30 KL30 LINBUS LINBUS KL31 KL31 Figure 2. Typical Application Diagram for a Master Node Table 1. PIN DESCRIPTION Pin Name Description 1 RxD Receive Data Output Low in Dominant State OpenDrain Output 2 EN Enable Input, Transceiver in Normal Operation Mode when High, Pulldown Resistor to GND 3 NC Not Connected 4 TxD Transmit Data Input, Low for Dominant State, Pulldown to GND 5 GND Ground 6 LIN LIN Bus Output/Input 7 V Battery Supply Input BB 8 NC Not Connected EP Exposed Pad. Recommended to connect to GND or left floating in application (DFN8 package only). www.onsemi.com 2 1 nF 1 k NCV7329 10 F 10 k 100 nF Microcontroller 220 pF NCV7329 10 F 10 k 100 nF Microcontroller