Automotive Grade Non-Synchronous Boost Controller NCV887200 The NCV887200 is an adjustable output nonsynchronous boost www.onsemi.com controller which drives an external Nchannel MOSFET. The device uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that supplies charge to the gate MARKING driver. DIAGRAM Protection features include internallyset softstart, undervoltage 8 lockout, cyclebycycle current limiting, hiccupmode shortcircuit SOIC8 887200 protection and thermal shutdown. D SUFFIX ALYW 8 Additional features include low quiescent current sleep mode and CASE 751 1 externallysynchronizable switching frequency. 1 Features 887200 = Specific Device Code A = Assembly Location Peak Current Mode Control with Internal Slope Compensation L = Wafer Lot 1.2 V 2% Reference voltage Y = Year Fixed Frequency Operation W = Work Week = PbFree Package Wide Input Voltage Range of 4.8 V to 40 Vdc, 45 V Load Dump Input Undervoltage Lockout (UVLO) Extended UVLO Hysteresis Allows Continuous Operation with a PIN CONNECTIONS Reverse Polarity Protection Diode Internal SoftStart EN/SYNC 1 8 VFB Low Quiescent Current in Sleep Mode 2 ISNS 7 VC CyclebyCycle Current Limit Protection 3 GND 6 VIN HiccupMode Overcurrent Protection (OCP) 4 HiccupMode ShortCircuit Protection (SCP) GDRV 5 VDRV Thermal Shutdown (TSD) (Top View) This is a PbFree Device NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 ORDERING INFORMATION Qualified and PPAP Capable Device Package Shipping NCV887200D1R2G SOIC8 2500 / Tape & (PbFree) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: September, 2019 Rev. 11 NCV887200/DNCV887200 V g VIN 6 TEMP C L VDRV g C DRV FAULT D VDRV LOGIC 5 V o CLK EN/ EN/SYNC OSC GDRV Q 1 DRIVE 4 SYNC LOGIC SC ISNS 2 C o CL R CSA SNS GND VC 7 3 + R SCP R F1 C VFB 8 C C Gm R F2 SS V ref Figure 1. Simplified Block Diagram and Application Schematic PACKAGE PIN DESCRIPTIONS Pin Symbol Pin No. Function 1 EN/SYNC Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled into sleep mode when this pin is brought low for longer than the enable timeout period. 2 ISNS Current sense input. Connect this pin to the source of the external NMOSFET, through a currentsense resistor to ground to sense the switching current for regulation and current limiting. 3 GND Ground reference. 4 GDRV Gate driver output. Connect to gate of the external N MOSFET. A series resistance can be added from GDRV to the gate to tailor EMC performance. An R = 15 k (typical) GDRVGND resistor is strongly GND recommended. 5 VDRV Driving voltage. Internally regulated supply for driving the external N MOSFET, sourced from VIN. Bypass with a 1.0 F ceramic capacitor to ground. 6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addi- tion to a diode from the output voltage to VDRV and/or VIN. 7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize the converter. 8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND creates a voltage divider for regulation and programming of the output voltage. www.onsemi.com 2 PWM